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59 条记录 (耗时 0.032 秒)

    System and method for disconnecting a portion of an integrated circuit
    31.
    发明授权
    System and method for disconnecting a portion of an integrated circuit 失效

    公开(公告)号：US07057866B2

    公开(公告)日：2006-06-06

    申请号：US09929591

    申请日：2001-08-14

    申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Chorng-Lii Hwang ,  Toshiaki K. Kirihata ,  Paul C. Parries

    发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Chorng-Lii Hwang ,  Toshiaki K. Kirihata ,  Paul C. Parries

    IPC分类号： G11C8/00

    CPC分类号： G11C5/14 ,  G11C5/147

    摘要： An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.

    Low power manager for standby operation of memory system
    32.
    发明授权
    Low power manager for standby operation of memory system 有权
    低功耗管理器用于存储系统的待机操作

    公开(公告)号：US07046572B2

    公开(公告)日：2006-05-16

    申请号：US10250233

    申请日：2003-06-16

    申请人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    发明人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    IPC分类号： G11C7/00

    CPC分类号： G11C5/143 ,  G11C8/08

    摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

    摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

    METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT
    38.
    发明申请
    METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT 失效
    通过门式井口植入降低阈值电压变化的方法

    公开(公告)号：US20120326233A1

    公开(公告)日：2012-12-27

    申请号：US13608860

    申请日：2012-09-10

    申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

    摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

    摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部内。

    REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
    39.
    发明申请
    REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD 有权
    SOI结构和方法中减少的角膜泄漏

    公开(公告)号：US20110291169A1

    公开(公告)日：2011-12-01

    申请号：US12791372

    申请日：2010-06-01

    申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L27/12 ,  H01L21/86 ,  H01L29/78

    CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

    摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

    摘要翻译： 通过在沟槽中提供衬垫，切割有源半导体层中的导电沟道区域，蚀刻导电沟道的侧面，拐角和/或底部，其中底切暴露半导体材料来提供用于减少晶体管泄漏的复古掺杂的结构替代方案 在有源层中，用绝缘体代替导电沟道的去除部分。 传导通道的这种整形增加了相邻电路元件的距离，如果充电，电荷可能会导致电压并导致导通通道区域中的反向通道阈值的变化并且减小了通道的横截面积 通道的传导不能很好地控制; 这两种效应显着降低了晶体管的泄漏。

    DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP
    40.
    发明申请
    DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
    在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器

    公开(公告)号：US20110092043A1

    公开(公告)日：2011-04-21

    申请号：US12974451

    申请日：2010-12-21

    申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

    发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

    IPC分类号： H01L21/02

    CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

    摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

    摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。