Multi-level capacitive DAC
    32.
    发明授权
    Multi-level capacitive DAC 有权
    多电平电容DAC

    公开(公告)号:US08970415B2

    公开(公告)日:2015-03-03

    申请号:US14197401

    申请日:2014-03-05

    CPC classification number: H03M1/0665 H03M3/424 H03M3/464

    Abstract: A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.

    Abstract translation: 电荷转移型的数模转换器(DAC)可用于Σ-Δ调制器,用于产生N个输出电平,其中输出电平由DAC传输的相应电荷量定义。 DAC具有接收参考电压的第一电容器开关单元和用于传送第一输出电荷的第一数字输入值,接收参考电压的至少一个第二电容开关单元和第二数字输入值,其中第二电容器开关 单元与第一电容器开关单元的输出并联耦合以产生第一和第二传送输出电荷的总和; 以及控制第一和第二电容器开关单元的开关的定序器,其中为每个DAC输入值提供根据各个第一和第二数字输入值的开关序列以产生N个输出电平。

    Quantization Noise Coupling Delta Sigma ADC with a Delay in the Main DAC Feedback
    33.
    发明申请
    Quantization Noise Coupling Delta Sigma ADC with a Delay in the Main DAC Feedback 有权
    量化噪声耦合ΔΣADC在主DAC反馈中具有延迟

    公开(公告)号:US20140368365A1

    公开(公告)日:2014-12-18

    申请号:US14301948

    申请日:2014-06-11

    CPC classification number: H03M3/39 H03M3/30 H03M3/368 H03M3/496

    Abstract: A delta-sigma modulator has a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function, a second summing point adding an output signal from said transfer function to the input signal and subtracting a second feedback signal, a first integrator receiving an output signal from the second summing point, a quantizer receiving an output signal from the integrator and generating an output bitstream, and a digital-to-analog converter receiving the bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay.

    Abstract translation: Δ-Σ调制器具有从输入信号减去第一反馈信号并将结果转发到传递函数的第一求和点,将来自所述传递函数的输出信号加到输入信号的第二求和点,并且减去第二反馈信号 接收来自第二求和点的输出信号的第一积分器,接收来自积分器的输出信号并产生输出比特流的量化器以及接收比特流的数模转换器,其中第一和第二反馈信号是 来自所述数模转换器的输出信号延迟一个采样延迟。

    2-Phase Switched Capacitor Flash ADC
    35.
    发明申请
    2-Phase Switched Capacitor Flash ADC 有权
    2相开关电容闪存ADC

    公开(公告)号:US20140240155A1

    公开(公告)日:2014-08-28

    申请号:US14181904

    申请日:2014-02-17

    Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference

    Abstract translation: 用于开关电容器模拟 - 数字转换器的输入级具有接收输入电压的差分电压输入端,接收斩波参考电压的差分参考电压输入,公共电压连接和差分输出。 一对输入电容器耦合在差分电压输入和差分输出之间,一对参考电容耦合在差分参考电压输入端之间。 开关单元由在第一阶段期间可操作的第一和第二相控制,以将输入电容器的第一端与公共电压连接相连,并将参考电容器的第一端与反相的差分电压基准耦合; 并且在第二阶段期间,将输入电容器的第一端子与差分输入电压连接,并将参考电容器的第一端子与非反相差分电压基准

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