公开(公告)号：US20250117209A1

公开(公告)日：2025-04-10

申请号：US18774768

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Niccolò Izzo ,  Alessandro Orlando ,  Danilo Caraccio

IPC: G06F8/65 ,  G06F21/57 ,  H04L9/08

Abstract: Methods, systems, and devices related to firmware validation for firmware updates are disclosed. A controller can, in association with a firmware update of a memory module: determine whether first security information and first customer information of a manifest of a firmware package are valid using second security information and second customer information, respectively, stored by a non-volatile memory device of the memory module; determine whether a first public key of a first image of the firmware package is valid using a second public key of the manifest corresponding to the first image and associated with the first security information and the first customer information; and determine whether a third public key of a second image of the firmware package is valid using a fourth public key of the manifest corresponding to the second image and associated with the first security information and the first customer information.

公开(公告)号：US20250094343A1

公开(公告)日：2025-03-20

申请号：US18782147

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US12217824B2

公开(公告)日：2025-02-04

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Amitava Majumdar ,  Cagdas Dirik ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Danilo Caraccio ,  Niccolo′ Izzo ,  Elliott C. Cooper-Balis ,  Markus H. Geiger

IPC: G11C29/52 ,  G11C7/22 ,  G11C7/24

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US12216525B2

公开(公告)日：2025-02-04

申请号：US18137895

申请日：2023-04-21

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Alessandro Orlando ,  Danilo Caraccio ,  Roberto Izzi

IPC: G06F11/07 ,  G06F11/30

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

公开(公告)号：US12182413B2

公开(公告)日：2024-12-31

申请号：US17897813

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Yang Lu ,  Edmund Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Danilo Caraccio ,  Robert M. Walker

IPC: G06F11/07 ,  G06F3/06

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

公开(公告)号：US20240096438A1

公开(公告)日：2024-03-21

申请号：US18169610

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Greg S. Hendrix ,  Anandhavel Nagendrakumar ,  Krunal Patel ,  Kirthi Shenoy ,  Danilo Caraccio ,  Ankush Lal ,  Frank F. Ross ,  Adam D. Gailey

IPC: G11C29/52 ,  G11C29/00

CPC classification number: G11C29/52 ,  G11C29/76 ,  G11C29/789

Abstract: In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

公开(公告)号：US20240036762A1

公开(公告)日：2024-02-01

申请号：US18227216

申请日：2023-07-27

Applicant: Micron Technology, Inc.

Inventor： Edmund J. Gieske ,  Cagdas Dirik ,  Elliott C. Cooper-Balis ,  Robert M. Walker ,  Amitava Majumdar ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Niccolò Izzo ,  Danilo Caraccio ,  Markus H. Geiger

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0802 ,  G06F2212/60

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

公开(公告)号：US11886710B2

公开(公告)日：2024-01-30

申请号：US17552060

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G11C16/34 ,  G06F12/1009

CPC classification number: G06F3/0611 ,  G06F3/0616 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0683 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/1009 ,  G11C16/3495 ,  G06F3/0619 ,  G06F3/0634 ,  G06F2212/65

Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.

公开(公告)号：US11835992B2

公开(公告)日：2023-12-05

申请号：US17192602

申请日：2021-03-04

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Marco Dallabora ,  Daniele Balluchi ,  Paolo Amato ,  Luca Porzio

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1668 ,  G06F13/28 ,  G06F2213/28

Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.

公开(公告)号：US20230290427A1

公开(公告)日：2023-09-14

申请号：US18120086

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi ,  Niccolò Izzo ,  Alessandro Orlando

IPC: G11C29/56 ,  G06F21/44

CPC classification number: G11C29/56016 ,  G06F21/445

Abstract: A controller can be configured to enable a host to control media testing on a memory device. The interface between the host and the memory can be abstract, such that the host does not have direct control over the memory. Instead, the controller can provide translation between a host protocol, such as compute express link (CXL), and a memory protocol, such as a protocol to control a dual data rate (DDR) interface. The controller can enable media test capability discovery, configuration, and/or control for the host. The controller can enable media test result reporting from the memory to the host.