公开(公告)号：US20230041326A1

公开(公告)日：2023-02-09

申请号：US17397603

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Albert Fayrushin ,  Matthew J. King ,  Madison D. Drake

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/78 ,  H01L29/66

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

公开(公告)号：US20230017241A1

公开(公告)日：2023-01-19

申请号：US17933227

申请日：2022-09-19

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H01L27/11582 ,  H01L21/768

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

公开(公告)号：US11508746B2

公开(公告)日：2022-11-22

申请号：US16664280

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Christopher R. Ritchie ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11548 ,  G11C7/18 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.

公开(公告)号：US11495530B2

公开(公告)日：2022-11-08

申请号：US16864823

申请日：2020-05-01

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Jeffrey D. Runia ,  Matthew Holland ,  Chamunda N. Chamunda

IPC: H01L23/522 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11519 ,  G11C8/14 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  G11C7/18 ,  H01L27/11565

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11469249B2

公开(公告)日：2022-10-11

申请号：US17172956

申请日：2021-02-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  David H. Wells ,  John D. Hopkins ,  Kevin Y. Titus

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/08 ,  H01L29/10 ,  H01L21/28 ,  H01L29/66 ,  H01L21/321 ,  H01L29/45 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/82

Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

公开(公告)号：US20220199644A1

公开(公告)日：2022-06-23

申请号：US17691993

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Matthew J. King ,  John D. Hopkins ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L23/48

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

公开(公告)号：US20220068956A1

公开(公告)日：2022-03-03

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20220028881A1

公开(公告)日：2022-01-27

申请号：US16937303

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H01L27/11582 ,  H01L21/768

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

公开(公告)号：US20210343637A1

公开(公告)日：2021-11-04

申请号：US16864823

申请日：2020-05-01

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Jeffrey D. Runia ,  Matthew Holland ,  Chamunda N. Chamunda

IPC: H01L23/522 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  G11C7/18 ,  G11C8/14

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11101280B2

公开(公告)日：2021-08-24

申请号：US16728723

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  S.M. Istiaque Hossain ,  Darwin A. Clampitt ,  Arun Kumar Dhayalan ,  Kevin R. Gast ,  Christopher Larsen ,  Prakash Rau Mokhna Rau ,  Shashank Saraf

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11565 ,  H01L21/311

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b). At least one horizontally-elongated isolation structure is formed in the first and second insulator materials and in a top part of the stack in individual of the memory-block regions. Additional methods, including structure independent of method, are disclosed.