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    Systems and methods for improving write preambles in DDR memory devices
    31.
    发明授权
    Systems and methods for improving write preambles in DDR memory devices 有权

    公开(公告)号：US10510398B2

    公开(公告)日：2019-12-17

    申请号：US15826236

    申请日：2017-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

    IPC: G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4076

    Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

    System and method for individual addressing
    33.
    发明授权
    System and method for individual addressing 有权

    公开(公告)号：US10268602B2

    公开(公告)日：2019-04-23

    申请号：US15280611

    申请日：2016-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

    IPC: G06F12/02 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    Instruction insertion in state machine engines
    34.
    发明授权
    Instruction insertion in state machine engines 有权

    公开(公告)号：US09934034B2

    公开(公告)日：2018-04-03

    申请号：US14736052

    申请日：2015-06-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David R. Brown

    IPC: G06F9/30 ,  G06F9/38 ,  G05B19/045

    CPC classification number: G06F9/3005 ,  G05B19/045 ,  G06F9/3834

    Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.

    METHODS AND SYSTEMS FOR USING STATE VECTOR DATA IN A STATE MACHINE ENGINE
    37.
    发明申请
    METHODS AND SYSTEMS FOR USING STATE VECTOR DATA IN A STATE MACHINE ENGINE 审中-公开
    在状态机发动机中使用状态矢量数据的方法和系统

    公开(公告)号：US20160320982A1

    公开(公告)日：2016-11-03

    申请号：US15206824

    申请日：2016-07-11

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B Noyes

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0664 ,  G06F3/0673 ,  G06F8/42 ,  G06N3/02

    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

    Abstract translation: 状态机引擎包括状态向量系统。 状态向量系统包括：输入缓冲器，被配置为从恢复缓冲器接收状态向量数据，并向状态机格状态提供状态向量数据。 状态向量系统还包括：输出缓冲器，被配置为从状态机格点接收状态向量数据，并向保存缓冲器提供状态向量数据。

    METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINE
    39.
    发明申请
    METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINE 审中-公开
    用于处理状态机发动机接收的数据的方法和系统

    公开(公告)号：US20160124860A1

    公开(公告)日：2016-05-05

    申请号：US14992616

    申请日：2016-01-11

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit Singh Bains

    IPC: G06F12/08 ,  G06F3/06

    CPC classification number: G06F12/0875 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0683 ,  G06F9/4498 ,  G06F2212/60 ,  G06N3/02

    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

    Abstract translation: 数据分析系统分析数据。 数据分析系统包括被配置为接收待分析数据的数据缓冲器。 数据分析系统还包括状态机格。 状态机格子包括多个数据分析元素，并且每个数据分析元件包括配置成分析数据的至少一部分并输出分析结果的多个存储器单元。 数据分析系统包括配置成从数据缓冲器接收数据并将数据提供给状态机格的缓冲接口。

    COUNTER OPERATION IN A STATE MACHINE LATTICE
    40.
    发明申请
    COUNTER OPERATION IN A STATE MACHINE LATTICE 有权
    状态机计数器中的计数器运行

    公开(公告)号：US20150253755A1

    公开(公告)日：2015-09-10

    申请号：US14722941

    申请日：2015-05-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G05B19/045 ,  H03K19/177

    CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不多于）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。

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