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    Coherency issue resolution in logical to physical page translation in a memory sub-system
    32.
    发明授权
    Coherency issue resolution in logical to physical page translation in a memory sub-system 有权

    公开(公告)号：US11157193B2

    公开(公告)日：2021-10-26

    申请号：US16715986

    申请日：2019-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Peng Xu ,  Jiangang Wu ,  Yun Li

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1009

    Abstract: A write request to program data to a memory device of a memory sub-system is received. An intermediate entry of a data structure is generated, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. A read request to read the data from the memory device is received and a look-up operation of the data structure is performed to identify the intermediate entry. Using the pointer to locate the write buffer associated with the intermediate write operation. The write buffer is copied to a read buffer associated with the read request and the read request is executed using the read buffer.

    Memory sub-system write sequence track
    33.
    发明授权
    Memory sub-system write sequence track 有权

    公开(公告)号：US12182013B2

    公开(公告)日：2024-12-31

    申请号：US18519311

    申请日：2023-11-27

    Applicant: Micron Technology, Inc.

    Inventor： Karl D. Schuh ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Kishore K. Muchherla

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/0882

    Abstract: A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

    Memory sub-system management based on dynamic control of wordline start voltage
    34.
    发明授权
    Memory sub-system management based on dynamic control of wordline start voltage 有权

    公开(公告)号：US11915785B2

    公开(公告)日：2024-02-27

    申请号：US17415657

    申请日：2021-01-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jiangang Wu ,  Lei Zhou ,  Jung Sheng Hoei ,  Kishore Kumar Muchherla ,  Qisong Lin

    IPC: G11C16/10 ,  G11C7/10 ,  G11C8/08 ,  G11C8/14

    CPC classification number: G11C7/1096 ,  G11C8/08 ,  G11C8/14 ,  G11C16/10

    Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.

    Memory die resource management
    37.
    发明授权
    Memory die resource management 有权

    公开(公告)号：US11756626B2

    公开(公告)日：2023-09-12

    申请号：US17520398

    申请日：2021-11-05

    Applicant: Micron Technology, Inc.

    Inventor： Jiangang Wu ,  James P. Crowley ,  Yun Li

    IPC: G11C16/26 ,  G11C16/14 ,  G06F12/02 ,  G06F9/50

    CPC classification number: G11C16/14 ,  G06F9/5016 ,  G06F12/0246 ,  G11C16/26 ,  G06F2209/503 ,  G06F2209/508

    Abstract: Methods, systems, and devices for memory die resource management are described. A resource manager can determine, from a set of global resources for multiple memory dies of a memory sub-system, a set of die-specific resources for a memory die of the multiple memory dies of the memory sub-system. In some case, the set of die-specific resources can be allocated for read commands for the memory die. The resource manager can assign a read command to a die-specific resource of the set of die-specific resources based on the die-specific resource being available and refrain from assigning the read command to the die-specific resource based on the die-specific resource being unavailable.

    Full multi-plane operation enablement
    40.
    发明授权
    Full multi-plane operation enablement 有权

    公开(公告)号：US11615029B2

    公开(公告)日：2023-03-28

    申请号：US16730881

    申请日：2019-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

    IPC: G06F11/00 ,  G06F12/0891 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/14 ,  G11C16/06 ,  G06F13/16

    Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

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