公开(公告)号：US20200279604A1

公开(公告)日：2020-09-03

申请号：US16876641

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Mattia Robustelli ,  Innocenzo Tortorelli ,  Mario Allegra ,  Paolo Amato

IPC: G11C13/00 ,  G06F11/10 ,  G11C29/52

Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.

公开(公告)号：US10741243B2

公开(公告)日：2020-08-11

申请号：US16729061

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Alessandro Orlando

IPC: G11C11/22 ,  G11C11/56 ,  G11C16/32 ,  G11C16/30 ,  G11C8/14 ,  G11C16/08 ,  G11C13/00 ,  G11C7/14

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

公开(公告)号：US10607664B2

公开(公告)日：2020-03-31

申请号：US15928831

申请日：2018-03-22

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Paolo Amato ,  Marco Sforzin

IPC: G11C7/00 ,  G11C7/06 ,  G11C16/10 ,  G11C13/00 ,  G11C16/26

Abstract: An apparatus has an array of memory cells and a controller coupled to the array. The controller is configured to track a sub-threshold leakage current through a number of memory cells of the array and determine a threshold voltage based on the sub-threshold leakage current.

公开(公告)号：US10424372B1

公开(公告)日：2019-09-24

申请号：US15957173

申请日：2018-04-19

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G11C11/00 ,  G11C13/00

Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

公开(公告)号：US20160364294A1

公开(公告)日：2016-12-15

申请号：US14735803

申请日：2015-06-10

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1072 ,  G06F11/108 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/00

Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Abstract translation: 描述用于数据存储错误保护的装置和方法。 用于数据存储错误保护的一个示例性装置包括以第一维度和第二维度布置的存储器单元的阵列。 控制器被配置为确定对应于存储在存储器单元中的数据的一组符号。 控制器被配置为将倾斜地定向到第一维度和第二维度的符号集合的子集添加以确定奇偶校验符号的数量。 控制器被配置为使用相同数量的奇偶校验符号来保护与第一维平行定向的存储器单元的第一子集，用于保护平行于第二维定向的存储器单元定向的第二子集。

公开(公告)号：US20160085625A1

公开(公告)日：2016-03-24

申请号：US14491544

申请日：2014-09-19

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F9/00 ,  G06F11/00 ,  G06F11/108

Abstract: Methods and apparatus for Exclusive OR (XOR) programming of a memory device are described. A program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory.

Abstract translation: 描述了用于存储器件的异或（XOR）编程的方法和装置。 设备内部的程序使用XOR程序规则来计算奇偶校验或其他值。 在一些实施例中，程序生成并将奇偶校验结果直接存储在存储器件本身中，而不需要外部控制器的干预。 在存储器件中产生奇偶校验的方法包括执行内部自累积奇偶校验程序，其中通过将先前存储的奇偶校验信息叠加在辅助存储器系统中的新累积的奇偶校验信息来累积奇偶校验和。 在独立设备实施例中，接收到具有地址和输入数据参数的新命令“XOR程序”，使得在输入地址处读取存储的数据，并执行读取数据和新输入数据的异或运算。 计算结果写入内存。

公开(公告)号：US20140285240A1

公开(公告)日：2014-09-25

申请号：US14299693

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Marco Sforzin

IPC: H03K19/0185

CPC classification number: H03K19/018528 ,  H03K19/00

Abstract: Buffers, integrated circuits, apparatuses, and methods for adjusting drive strength of a buffer are disclosed. In an example apparatus, the buffer includes a driver. The driver includes a pull-up circuit coupled to a supply voltage node and an output node, and also includes a pull-down circuit coupled to a reference voltage node and the output node. A drive adjust circuit is coupled to at least one of the pull-up circuit and the pull-down circuit, with the drive adjust circuit configured to receive a feedback signal and, based at least in part on the feedback signal, adjust a current conducted through the at least one of the pull-up and pull-down circuits.

Abstract translation: 公开了用于调节缓冲器的驱动强度的缓冲器，集成电路，装置和方法。 在示例性装置中，缓冲器包括驱动器。 驱动器包括耦合到电源电压节点和输出节点的上拉电路，并且还包括耦合到参考电压节点和输出节点的下拉电路。 驱动调节电路被耦合到上拉电路和下拉电路中的至少一个，驱动调整电路被配置为接收反馈信号，并且至少部分地基于反馈信号调整传导的电流 通过上拉和下拉电路中的至少一个。

公开(公告)号：US20140098623A1

公开(公告)日：2014-04-10

申请号：US13644510

申请日：2012-10-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Marco Sforzin

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/50 ,  G11C2029/5004

Abstract: Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse.

Abstract translation: 本文公开了用于感测熔丝状态的装置和方法。 装置可以包括具有多个感测线的阵列。 多个单元可以耦合到多条感测线的感测线。 熔丝检测电路可以耦合到多条感测线的感测线并且被配置为从多个单元的单元接收感测电压。 感测电压可以至少部分地基于对应于多个单元的单元的熔丝的状态。 熔丝检测电路还可以被配置为将感测电压与参考电压进行比较，以提供指示熔丝状态的熔丝状态控制信号。

公开(公告)号：US20250130718A1

公开(公告)日：2025-04-24

申请号：US18889047

申请日：2024-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Antonino Caprì ,  Graziano Mirichigni ,  Marco Sforzin ,  Bryan David Kerstetter ,  John David Porter

IPC: G06F3/06

Abstract: A system performs operations including: storing a first value in a first memory location used for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing a second value in a second memory location, wherein the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location comprises a preset value corresponding to a first component of the plurality of components of the memory device; and executing, by the first component, the command.

公开(公告)号：US20250094343A1

公开(公告)日：2025-03-20

申请号：US18782147

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.