公开(公告)号：US10833206B2

公开(公告)日：2020-11-10

申请号：US16215929

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/94 ,  H01L27/11526 ,  H01L29/49 ,  H01L21/28 ,  G11C16/30 ,  H01L27/11573 ,  H01L29/66 ,  G11C16/04

Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

公开(公告)号：US20200185544A1

公开(公告)日：2020-06-11

申请号：US16215929

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/94 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  G11C16/30 ,  H01L27/11526 ,  H01L27/11573

Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

公开(公告)号：US20190386021A1

公开(公告)日：2019-12-19

申请号：US16553587

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay ,  Michael A. Smith ,  Brett D. Lowe

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11575 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/033

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures. Semiconductor device structures, semiconductor devices, and electronic systems are also described.

公开(公告)号：US20190371789A1

公开(公告)日：2019-12-05

申请号：US16543715

申请日：2019-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22 ,  H01L21/28

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US10446579B2

公开(公告)日：2019-10-15

申请号：US16183392

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay ,  Michael A. Smith ,  Brett D. Lowe

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures. Semiconductor device structures, semiconductor devices, and electronic systems are also described.

公开(公告)号：US20190267323A1

公开(公告)日：2019-08-29

申请号：US16409464

申请日：2019-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/522 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11548

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

公开(公告)号：US09536823B2

公开(公告)日：2017-01-03

申请号：US14308339

申请日：2014-06-18

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

Abstract translation: 导电结构包括多个导电台阶和至少部分地穿过其延伸的接触件，与多个导电台阶中的至少一个连通，并与至少另一导电台阶绝缘。 设备可以包括这种导电结构。 系统可以包括半导体器件和楼梯级导电结构，其具有延伸穿过楼梯级导电结构的台阶的多个触点。 形成导电结构的方法包括在通过导电结构的至少一个导电步骤形成的接触孔中形成接触。 在楼梯级导电结构中形成电连接的方法包括在通过楼梯级导电结构的每个步骤形成的接触孔中形成触点。

公开(公告)号：US09530837B2

公开(公告)日：2016-12-27

申请号：US14966927

申请日：2015-12-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/088 ,  H01L27/085 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract translation: 一些实施例包括具有第一和第二晶体管的集成电路。 第一晶体管比第二晶体管宽。 第一和第二晶体管分别具有第一和第二有源区。 电介质特征与第一有源区相关联并且分解第一有源区。 第二活性区域不会分解成与第一活性区域相同的程度。 一些实施例包括形成晶体管的方法。 形成第一和第二晶体管的有源区。 第一晶体管的有效面积比第二晶体管的有效面积宽。 电介质特征形成在第一晶体管的有源区中。 第一晶体管的有效面积被分解为与第二晶体管的有效面积不同的程度。 第一和第二晶体管的有源区同时掺杂。

公开(公告)号：US11901448B2

公开(公告)日：2024-02-13

申请号：US17886436

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7831 ,  H01L29/1033

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

公开(公告)号：US11881528B2

公开(公告)日：2024-01-23

申请号：US18079848

申请日：2022-12-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/40 ,  H01L21/266 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7833 ,  H01L21/266 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/402 ,  H01L29/66492

Abstract: An apparatus includes a substrate and a transistor disposed on the substrate. The transistor includes a source and a source contact disposed on the source. The transistor also includes a drain and a drain contact disposed on the drain. A gate is disposed between the source contact and the drain contact, and a screened region is disposed adjacent the source contact or the drain contact. The screened region corresponds to a lightly doped region. The screened region includes an implant screen configured to reduce an effective dose in the screened region so as to shift an acceptable dose range of the screened region to a higher dose range. The acceptable dose range corresponds to acceptable breakdown voltage values for the screened region.