公开(公告)号：US20210200435A1

公开(公告)日：2021-07-01

申请号：US15929883

申请日：2020-05-27

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller

IPC: G06F3/06

Abstract: An asynchronous power loss (APL) event is determined to occur. A first erased page (FEP) in a block of a memory device is determined and a last written page (LWP) is determined from the FEP. Data is read from the LWP and peer pages corresponding to the LWP. The data is copied to a temporary area in the memory device and a write pointer is incremented by a deterministic number of pages in the block. Data from the temporary area is copied to a page location in the block identified by the write pointer and the write pointer is incremented by the deterministic number of pages again. A host system is notified that the memory device is ready for a subsequent programming operation after the APL event.

公开(公告)号：US20210074374A1

公开(公告)日：2021-03-11

申请号：US17100582

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G06F12/02 ,  G11C29/52 ,  G11C29/50 ,  G11C16/04

Abstract: An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.

公开(公告)号：US20210027846A1

公开(公告)日：2021-01-28

申请号：US17035149

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  Xu Zhang ,  Jie Zhou

IPC: G11C16/26 ,  G06F11/10 ,  G06F11/07 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G11C16/34

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US20200219573A1

公开(公告)日：2020-07-09

申请号：US16820636

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G11C29/50 ,  G06F12/02 ,  G11C16/04 ,  G11C29/52

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.

公开(公告)号：US20200020407A1

公开(公告)日：2020-01-16

申请号：US16448502

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC: G11C16/26

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US10529433B1

公开(公告)日：2020-01-07

申请号：US16102092

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Gerald L. Cadloni ,  Gary F. Besinga ,  Michael G. Miller ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C29/52 ,  G11C16/26 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04

Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.

公开(公告)号：US10340016B2

公开(公告)日：2019-07-02

申请号：US15633377

申请日：2017-06-26

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Jung Sheng Hoei ,  Michael G. Miller ,  Roland J. Awusie ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Gary F. Besinga ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G11C16/34 ,  G11C11/56

Abstract: A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

公开(公告)号：US20180196705A1

公开(公告)日：2018-07-12

申请号：US15911490

申请日：2018-03-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, JR. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079

Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

公开(公告)号：US11923030B2

公开(公告)日：2024-03-05

申请号：US17888641

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42 ,  G11C29/50

CPC classification number: G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C29/50004 ,  G11C29/783

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.

公开(公告)号：US20240071553A1

公开(公告)日：2024-02-29

申请号：US17894528

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.