-
公开(公告)号：US20170169885A1
公开(公告)日：2017-06-15
申请号：US15444982
申请日：2017-02-28
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang , Feng Pan , Ramin Ghodsi , Mark A. Helm
IPC: G11C11/56
CPC classification number: G11C11/5642 , G11C7/14 , G11C29/021 , G11C29/028 , G11C2029/0409
Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
-
公开(公告)号：US09312022B1
公开(公告)日：2016-04-12
申请号：US14590344
申请日：2015-01-06
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang , Ramin Ghodsi
IPC: G11C7/22 , G11C11/4076 , G11C7/10 , G11C16/32 , G11C16/10 , G11C29/02 , G11C11/4093
CPC classification number: G11C7/22 , G11C7/106 , G11C7/1066 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C16/10 , G11C16/32 , G11C29/023 , G11C29/028 , G11C2029/0409
Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.
Abstract translation: 公开了用于存储器输入定时自校准的方法，用于输入定时自校准的装置和系统。 一种这样的方法包括将多个延迟微调设置顺序地编程到数据路径的延迟电路中。 数据路径可以包括耦合到延迟电路的数据锁存器。 时钟耦合到数据锁存器，将数据时钟数据插入数据锁存器。 数据的转换基本上与时钟的转换对齐。 在对每个延迟微调设置进行编程后，读取数据锁存器的输出。 在数据锁存器的第一输出状态和数据锁存器的第二输出状态之间确定边界，其中边界与多个延迟调整设置的特定延迟微调设置相关联。 特定的延迟调整设置被编程到延迟电路中。
-
公开(公告)号：US20140022847A1
公开(公告)日：2014-01-23
申请号：US14034266
申请日：2013-09-23
Applicant: Micron Technology, Inc.
Inventor： Ramin Ghodsi , Qiang Tang
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/12
Abstract: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.
Abstract translation: 一种对非易失性存储单元中的浮置栅极进行充电的方法包括：使存储单元内的衬底沟道达到第一电压，使控制栅极达到编程电压，并且在控制栅极处于编程电压的同时浮置衬底沟道电压 。 存储器件包括可操作以执行所述方法的状态机或控制器，并描述了这种状态机，存储器件和信息处理系统的操作。
-
公开(公告)号：US20230031083A1
公开(公告)日：2023-02-02
申请号：US17966619
申请日：2022-10-14
Applicant: Micron Technology, Inc.
Inventor： Paolo Tessariol , Qiang Tang
IPC: H01L49/02 , H01L27/112 , H01L23/535 , H01L21/768 , H01L23/522
Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.
-
公开(公告)号：US11489038B2
公开(公告)日：2022-11-01
申请号：US15689735
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Paolo Tessariol , Qiang Tang
IPC: H01L49/02 , H01L27/112 , H01L23/535 , H01L21/768 , H01L23/522
Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.
-
Patent Agency Ranking
公开(公告)号：US20210166767A1
公开(公告)日：2021-06-03
申请号：US17176345
申请日：2021-02-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Xiaojiang Guo , Guanglei An , Qiang Tang
Abstract: Methods of operating a memory, and memories having a controller configured to cause the memory to perform such methods, include applying a plurality of first voltage levels to an access line, applying a plurality of second voltage levels to a control gate of a string driver connected to the access line for a first portion of the plurality of first voltage levels with each second voltage level of the plurality of second voltage levels being greater than a respective first voltage level by a first voltage differential, and applying a plurality of third voltage levels to the control gate of the string driver for a second portion of the plurality of first voltage levels with each third voltage level of the plurality of third voltage levels being greater than a respective first voltage level by a second voltage differential less than the first voltage differential.
-
公开(公告)号：US20210110856A1
公开(公告)日：2021-04-15
申请号：US17247267
申请日：2020-12-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kaveh Shakeri , Ali Feiz Zarrin Ghalam , Qiang Tang , Eric N. Lee
Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.
-
公开(公告)号：US10972078B2
公开(公告)日：2021-04-06
申请号：US16920315
申请日：2020-07-02
Applicant: Micron Technology, Inc.
Inventor： Guan Wang , Qiang Tang , Ali Feiz Zarrin Ghalam
IPC: G06F1/10 , H03K3/017 , H04L25/06 , H03K5/156 , G11C7/22 , G11C29/02 , H04L7/00 , H04L25/02 , G06F1/04
Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
-
公开(公告)号：US20210065807A1
公开(公告)日：2021-03-04
申请号：US17096055
申请日：2020-11-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Ramin Ghodsi
Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.
-
公开(公告)号：US10930321B2
公开(公告)日：2021-02-23
申请号：US16417528
申请日：2019-05-20
Applicant: Micron Technology, Inc.
Inventor： Xiaojiang Guo , Qiang Tang
IPC: G11C16/24 , G11C5/14 , G11C16/30 , G11C11/4074
Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.
-
-
-
-
-
-
-
-
-
Search Results
103
records
(took 0.021 seconds)
