公开(公告)号：US20240297124A1

公开(公告)日：2024-09-05

申请号：US18593504

申请日：2024-03-01

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Lance David Williamson ,  Kaveri Jain ,  Adam Lewis Olson

IPC: H01L23/544 ,  H01L21/308

CPC classification number: H01L23/544 ,  H01L21/308 ,  H01L2223/54426

Abstract: A memory device can include a substrate and a first alignment mark embedded in the substrate. The first alignment mark can be configured to a reference for a patterned second masking layer which is different from a first masking layer deposited on the substrate, and onto which the second patterned masking layer is deposited. The first masking layer can be an opaque or semi-opaque sacrificial layer and a second alignment mark can comprise at least a portion of the first masking layer. A location of the second alignment mark can correspond to a particular structure location in the substrate. The patterned second masking layer can include an additional alignment mark that is spaced laterally apart from the second alignment mark and the patterned second masking layer can define one or more locations of one or more structural features in the substrate.

公开(公告)号：US20240257875A1

公开(公告)日：2024-08-01

申请号：US18420201

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Richard T. Housley ,  Quinn L. Roberts ,  Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Tien Minh Quan Tran ,  Zhen Feng Yow ,  Wei Deng Leong ,  Kah Sing Chooi ,  Nils Monserud

IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers of different compositions relative one another. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. A registration mark is formed in the scribe-line area. The registration mark comprises parallel first bars atop the stack having first spaces therebetween. A masking material is directly above the stack, the first bars, and the first spaces. The masking material comprises parallel second bars having second spaces therebetween. The second spaces individually have width that is less than width of individual of the second bars. Some of the masking material is spaced laterally-outward of the second bars. Vertical thickness of the some masking material that is laterally-outward of the second bars have a vertical thickness laterally-outward of the first spaces that is greater than vertical thickness of the second bars. Ratio of the vertical thickness of the some masking material that is laterally-outward of the second bars divided by the width of the second bars is 6.0 to 9.6. After forming the registration mark, the first bars and the first and second tiers in the scribe-line area are cut through to form individual die that individually comprise one of the individual die areas. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240074194A1

公开(公告)日：2024-02-29

申请号：US18237661

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Harsh Narendrakumar Jain ,  Richard T. Housley ,  Zhenxing Han ,  Scott L. Light ,  Qinglin Zeng ,  Hsiao-Kuan Yuan ,  Jordan Chess ,  Xiaosong Zhang

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another; a first staircase structure formed in the tiers; a second staircase structure formed in the tiers adjacent the first staircase structure, respective portions of conductive materials in the tiers forming a part of the first and second staircase structure and a part of respective control gates associated with memory cells; a first trench structure formed in the tiers adjacent the first staircase structure and the second staircase structure, the first trench structure including length in a direction from the first staircase structure to the second staircase structure; and a second trench structure formed in the tiers adjacent the first trench structure, the second trench structure including a length in the direction from the first staircase structure to the second staircase structure.

公开(公告)号：US20240029795A1

公开(公告)日：2024-01-25

申请号：US17868232

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Lifang Xu ,  Harsh Narendrakumar Jain

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises channel-material strings of memory cells extending through insulative tiers and conductive tiers in a memory-array region. The insulative and conductive tiers extend from the memory-array region into a stair-step region. A plurality of stair-step structures is in the stair-step region. The stair-step structures individually comprise two opposing flights of stairs. The stair-step structures comprise an SGD stair-step structure and non-SGD stair-step structures. At least one of the non-SGD stair-step structures has less total stairs than are in individual of multiple others of the non-SGD stair-step structures. Other embodiments, including method, are disclosed.

公开(公告)号：US20230395513A1

公开(公告)日：2023-12-07

申请号：US17865565

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Yiping Wang ,  Jordan Chess ,  Collin Howder

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions. After the removing, the other of the first and second regions is used as a mask while etching through one of the first tiers and one of the second tiers in the individual stairs to form multiple different-depth treads in the individual stairs in a second vertical cross-section along the second direction. Other embodiments, including structure, are disclosed.

公开(公告)号：US11637178B2

公开(公告)日：2023-04-25

申请号：US17078755

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Harsh Narendrakumar Jain

IPC: H01L29/06 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230009880A1

公开(公告)日：2023-01-12

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：US20220077178A1

公开(公告)日：2022-03-10

申请号：US17016039

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Kaiming Luo ,  Sarfraz Qureshi ,  Md Zakir Ullah ,  Jessica Low Jing Wen ,  Harsh Narendrakumar Jain ,  Kok Siak Tang ,  Indra V. Chary ,  Matthew J. King

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and devices the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending the through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed.

公开(公告)号：US11101210B2

公开(公告)日：2021-08-24

申请号：US16664618

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Harsh Narendrakumar Jain ,  Matthew J. King

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

公开(公告)号：US20240373636A1

公开(公告)日：2024-11-07

申请号：US18621738

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David H. Wells ,  Yiping Wang ,  Mojtaba Asadirad ,  Harsh Narendrakumar Jain

IPC: H10B43/27 ,  H10B41/27

Abstract: A method of forming a microelectronic device comprises forming a preliminary stack structure over a source structure. The preliminary stack structure comprises a vertically alternating sequence of insulative material and sacrificial material arranged in preliminary tiers. The method comprises forming a staircase structure having steps comprising edges of at least some of the preliminary tiers of the preliminary stack structure, forming implant regions within exposed portions of the sacrificial material at the steps of the staircase structure, forming openings extending through the preliminary stack structure to the source structure and within a horizontal area of the staircase structure, replacing portions of the sacrificial material with conductive structures, forming strapping structures comprising conductive material, at locations vacated by the implant regions, laterally adjacent to the conductive structures at the steps of the staircase structure, and forming conductive contacts within the openings. Additional methods and microelectronic devices are also described.