公开(公告)号：US10747614B2

公开(公告)日：2020-08-18

申请号：US16042812

申请日：2018-07-23

Applicant: Micron Technology, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu ,  Zhengang Chen

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/29 ,  H03M13/37

Abstract: Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components.

公开(公告)号：US20200026602A1

公开(公告)日：2020-01-23

申请号：US16042812

申请日：2018-07-23

Applicant: Micron Technology, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu ,  Zhengang Chen

IPC: G06F11/10 ,  H03M13/37 ,  H03M13/29

Abstract: Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components.

公开(公告)号：US12301254B2

公开(公告)日：2025-05-13

申请号：US17829913

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Yoav Weinberg ,  Zhengang Chen ,  Sivagnanam Parthasarathy

IPC: H03M13/11

Abstract: A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

公开(公告)号：US12086058B2

公开(公告)日：2024-09-10

申请号：US18206958

申请日：2023-06-07

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G11C11/56 ,  H04L9/06 ,  H04L9/08

CPC classification number: G06F12/0246 ,  G06F12/1408 ,  G06F13/1668 ,  G11C11/5628 ,  H04L9/0662 ,  H04L9/0869 ,  G06F2212/7207

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US11914510B2

公开(公告)日：2024-02-27

申请号：US17736824

申请日：2022-05-04

Applicant: Micron Technology Inc.

Inventor： Mikai Chen ,  Zhengang Chen ,  Charles See Yeung Kwong

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0607 ,  G06F12/0207 ,  G06F2212/1032

Abstract: In a memory sub-system, data can be received to be stored at a 3-dimensional (3D) memory component in response to a write operation. A first location of a first layer of the 3D memory component is determined at which to store a first portion of the data, where the first layer is within a first logical unit. A second location of a second layer of the 3D memory component is determined at which to store a second portion of the data, where the second layer is within a second logical unit that is different than the first logical unit. The first portion of the data is caused to be stored in first memory cells at the first location within the first layer. The second portion of the data is caused to be stored in second memory cells at the second location within the second layer.

公开(公告)号：US11870461B2

公开(公告)日：2024-01-09

申请号：US17880144

申请日：2022-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wei Wu ,  Zhenlei Shen ,  Zhengang Chen

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/1525 ,  G06F11/1076

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.

公开(公告)号：US20230396271A1

公开(公告)日：2023-12-07

申请号：US17829913

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Yoav Weinberg ,  Zhengang Chen ,  Sivagnanam Parthasarathy

IPC: H03M13/11

CPC classification number: H03M13/1117 ,  H03M13/1108 ,  H03M13/1151

Abstract: A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

公开(公告)号：US20230359388A1

公开(公告)日：2023-11-09

申请号：US17735458

申请日：2022-05-03

Applicant: Micron Technology, Inc.

Inventor： Dung Viet Nguyen ,  Patrick R. Khayat ,  Zhengang Chen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metadata characterizing voltage distributions. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: receiving one or more metadata values characterizing threshold voltage distributions of a subset of the plurality of memory cells connected to one or more bitlines, wherein the one or more metadata values reflect a conductive state of the one or more bitlines; determining a read voltage adjustment value based on the one or more metadata values; and applying the read voltage adjustment value for reading the subset of the plurality of memory cells.

公开(公告)号：US11750218B2

公开(公告)日：2023-09-05

申请号：US17831357

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/1128 ,  G06F11/1076

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

公开(公告)号：US20230082008A1

公开(公告)日：2023-03-16

申请号：US17991408

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Zhengang Chen

IPC: G06F3/06

Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.