公开(公告)号：US07679134B1

公开(公告)日：2010-03-16

申请号：US10754515

申请日：2004-01-12

Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

IPC: H01L29/94

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L29/66795

Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

Abstract translation: 半导体器件包括一组翅片结构。 翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。 半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

公开(公告)号：US07179692B2

公开(公告)日：2007-02-20

申请号：US10913409

申请日：2004-08-09

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.

Abstract translation: 形成半导体器件的方法包括在绝缘层上形成翅片，其中鳍片包括多个侧表面，顶表面和底表面。 该方法还包括在绝缘层上形成栅极，其中栅极在半导体器件的沟道区域具有基本上U形的横截面。

公开(公告)号：US07095065B2

公开(公告)日：2006-08-22

申请号：US10633504

申请日：2003-08-05

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

IPC: H01L29/80

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.

Abstract translation: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 第一器件可以形成在绝缘层上，包括第一鳍片。 第一翅片可以形成在绝缘层上，并且可以具有第一翅片长宽比。 第二装置可以形成在绝缘层上，包括第二鳍片。 第二翅片可以形成在绝缘层上，并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

公开(公告)号：US06911697B1

公开(公告)日：2005-06-28

申请号：US10632965

申请日：2003-08-04

Applicant: Haihong Wang ,  Judy Xilin An ,  Bin Yu

Inventor： Haihong Wang ,  Judy Xilin An ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin, source and drain regions and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The source region is formed on the insulating layer adjacent a first side of the fin and the drain region is formed on the second side of the fin opposite the first side. The source and drain regions have a greater thickness than the fin in the channel region of the semiconductor device.

Abstract translation: 双栅极半导体器件包括衬底，绝缘层，鳍，源极和漏极区以及栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 源极区域形成在与鳍片的第一侧相邻的绝缘层上，并且漏极区域形成在与第一侧相对的翅片的第二侧上。 源极和漏极区域具有比半导体器件的沟道区域中的鳍片更大的厚度。

公开(公告)号：US20050118824A1

公开(公告)日：2005-06-02

申请号：US11030191

申请日：2005-01-07

Applicant: Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: C09G1/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/84

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Abstract translation: 制造MOSFET型半导体器件的方法包括平坦化沉积在沟道上的栅极材料层。 平面化在包括初始“粗糙”平坦化然后是“精细”平坦化的多步骤过程中进行。 用于更精细平坦化的浆料可以包括倾向于粘附到栅极材料的低区域的添加材料。

公开(公告)号：US20050006666A1

公开(公告)日：2005-01-13

申请号：US10913409

申请日：2004-08-09

Applicant: Bin Yu ,  Shibly Ahmed ,  Judy An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly Ahmed ,  Judy An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L31/072

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.

Abstract translation: 形成半导体器件的方法包括在绝缘层上形成翅片，其中鳍片包括多个侧表面，顶表面和底表面。 该方法还包括在绝缘层上形成栅极，其中栅极在半导体器件的沟道区域具有基本上U形的横截面。

公开(公告)号：US06716690B1

公开(公告)日：2004-04-06

申请号：US10385692

申请日：2003-03-12

Applicant: Haihong Wang ,  Judy Xilin An ,  Bin Yu

Inventor： Haihong Wang ,  Judy Xilin An ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L29/458 ,  H01L29/66795 ,  Y10S438/914

Abstract: Multiple dopant implantations are performed on a FinFET device to thereby distribute the dopant in a substantially uniform manner along a vertical depth of the FinFET in the source/drain junction. Each of the multiple implantations may be performed at different tilt angles.

Abstract translation: 在FinFET器件上执行多个掺杂剂注入，从而沿着源极/漏极结中的FinFET的垂直深度以大致均匀的方式分布掺杂剂。 多个注入中的每一个可以以不同的倾斜角执行。

公开(公告)号：US06709982B1

公开(公告)日：2004-03-23

申请号：US10303702

申请日：2002-11-26

Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Haihong Wang ,  Bin Yu

IPC: H01L21311

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L29/66795

Abstract: A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.

Abstract translation: 一种在半导体器件中形成一组结构的方法包括在基底上形成导电层，其中导电层包括导电材料，并在导电层上形成氧化物层。 该方法还包括蚀刻氧化物层中的至少一个开口，用导电材料填充至少一个开口，蚀刻导电材料以在至少一个开口的侧壁上形成间隔物，并且去除氧化物层和一部分 导电层形成一组结构。

公开(公告)号：US08217450B1

公开(公告)日：2012-07-10

申请号：US10770011

申请日：2004-02-03

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

IPC: H01L29/94

CPC classification number: H01L29/785 ,  H01L29/7855 ,  H01L29/7856

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is adjacent a first sidewall of the fin. The second gate is formed on the insulating layer and is adjacent a second sidewall of the fin opposite the first sidewall. The first and second gates both include a conductive material and are electrically separated by the fin.

Abstract translation: 双栅半导体器件包括衬底，绝缘层，鳍和两个栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 第一栅极形成在绝缘层上并与鳍片的第一侧壁相邻。 第二栅极形成在绝缘层上并且与第一侧壁相对的翅片的第二侧壁相邻。 第一和第二栅极都包括导电材料并且被散热片电隔离。

公开(公告)号：US07112847B1

公开(公告)日：2006-09-26

申请号：US10653227

申请日：2003-09-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  Y10S257/90

Abstract: A semiconductor device includes a semiconductor fin formed on an insulator and sidewall spacers formed adjacent the sides of the fin. A gate material layer is formed over the fin and the sidewall spacers and etched to form a gate. The presence of the sidewall spacers causes a topology of the gate material layer to smoothly transition over the fin and the first and second sidewall spacers.

Abstract translation: 半导体器件包括形成在绝缘体上的半导体鳍片和邻近翅片侧面形成的侧壁间隔物。 栅极材料层形成在鳍片和侧壁间隔物上并被蚀刻以形成栅极。 侧壁间隔物的存在导致栅极材料层的拓扑结构平滑地过渡翅片和第一和第二侧壁间隔物。