公开(公告)号：US08084760B2

公开(公告)日：2011-12-27

申请号：US12426809

申请日：2009-04-20

申请人： Hsiang-Lan Lung ,  Shih-Hung Chen ,  Stephen M. Rossnagel

发明人： Hsiang-Lan Lung ,  Shih-Hung Chen ,  Stephen M. Rossnagel

IPC分类号： H01L29/02

CPC分类号： H01L45/142 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： An electrode structure and a method for manufacturing an integrated circuit electrode includes forming a bottom electrode comprising a pipe-shaped member, filled with a conductive material such as n-doped silicon, and having a ring-shaped top surface. A disc-shaped insulating member is formed on the top of the pipe-shaped member by oxidizing the conductive fill. A layer of programmable resistance material, such as a phase change material, is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistance material.

摘要翻译： 电极结构和集成电路电极的制造方法包括形成包含管状部件的底部电极，该管状部件填充有诸如n掺杂硅的导电材料，并具有环形顶表面。 通过氧化导电填料，在管状构件的顶部上形成圆盘形的绝缘构件。 将一层可编程电阻材料（例如相变材料）沉积成与管状构件的顶表面接触。 与可编程电阻材料层接触的顶部电极。

公开(公告)号：US07956463B2

公开(公告)日：2011-06-07

申请号：US12560878

申请日：2009-09-16

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Stephen M. Rossnagel

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Stephen M. Rossnagel

IPC分类号： H01L23/48

CPC分类号： H01L21/76871 ,  H01L21/76846 ,  H01L21/76868 ,  H01L21/76883

摘要： An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.

摘要翻译： 提供具有降低的电阻的互连结构和形成这种互连结构的方法。 互连结构包括其中包括至少一个开口的电介质材料。 至少一个开口填充有可选的阻挡扩散层，晶粒生长促进层，聚集的电镀种子层，任选的第二电镀种子层，导电结构。 包含含金属的导电材料（通常为Cu）的导电结构具有竹结构，平均晶粒尺寸大于0.05微米。 在一些实施例中，导电结构包括具有（111）晶体取向的导电晶粒。

公开(公告)号：US20110062587A1

公开(公告)日：2011-03-17

申请号：US12560878

申请日：2009-09-16

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Stephen M. Rossnagel

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Stephen M. Rossnagel

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76871 ,  H01L21/76846 ,  H01L21/76868 ,  H01L21/76883

摘要： An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer, a grain growth promotion layer, an agglomerated plating seed layer, an optional second plating seed layer a conductive structure. The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.

摘要翻译： 提供具有降低的电阻的互连结构和形成这种互连结构的方法。 互连结构包括其中包括至少一个开口的电介质材料。 至少一个开口填充有可选的阻挡扩散层，晶粒生长促进层，聚集的电镀种子层，任选的第二电镀种子层，导电结构。 包含含金属的导电材料（通常为Cu）的导电结构具有竹结构，平均晶粒尺寸大于0.05微米。 在一些实施例中，导电结构包括具有（111）晶体取向的导电晶粒。

公开(公告)号：US20100025249A1

公开(公告)日：2010-02-04

申请号：US12540553

申请日：2009-08-13

申请人： Stanislav Polonsky ,  Stephen M. Rossnagel ,  Gustavo A. Stolovitzky

发明人： Stanislav Polonsky ,  Stephen M. Rossnagel ,  Gustavo A. Stolovitzky

IPC分类号： B01D61/46

CPC分类号： G01N33/48721 ,  B82Y15/00 ,  B82Y30/00 ,  C12Q1/6825 ,  C12Q1/6869 ,  G01N2015/0038 ,  Y10S977/924 ,  C12Q2565/631 ,  C12Q2565/607 ,  C12Q2563/155

摘要： Techniques for controlling the position of a charged polymer inside a nanopore are provided. For example, one technique includes using electrostatic control to position a linear charged polymer inside a nanopore, and creating an electrostatic potential well inside the nanopore, wherein the electrostatic potential well controls a position of the linear charged polymer inside the nanopore.

摘要翻译： 提供了用于控制纳米孔内带电聚合物位置的技术。 例如，一种技术包括使用静电控制将线性带电聚合物定位在纳米孔内，并在纳米孔内产生静电势阱，其中静电势阱控制纳米孔内线性带电聚合物的位置。

公开(公告)号：US20080187915A1

公开(公告)日：2008-08-07

申请号：US11670621

申请日：2007-02-02

申请人： Stanislav Polonsky ,  Stephen M. Rossnagel ,  Gustavo A. Stolovitzky

发明人： Stanislav Polonsky ,  Stephen M. Rossnagel ,  Gustavo A. Stolovitzky

IPC分类号： C12Q1/68 ,  G01N27/30

CPC分类号： G01N33/48721 ,  B82Y15/00 ,  B82Y30/00 ,  C12Q1/6825 ,  C12Q1/6869 ,  G01N2015/0038 ,  Y10S977/924 ,  C12Q2565/631 ,  C12Q2565/607 ,  C12Q2563/155

摘要： Techniques for controlling the position of a charged polymer inside a nanopore are provided. For example, one technique includes using electrostatic control to position a linear charged polymer inside a nanopore, and creating an electrostatic potential well inside the nanopore, wherein the electrostatic potential well controls a position of the linear charged polymer inside the nanopore.

摘要翻译： 提供了用于控制纳米孔内带电聚合物位置的技术。 例如，一种技术包括使用静电控制将线性带电聚合物定位在纳米孔内，并在纳米孔内产生静电势阱，其中静电势阱控制纳米孔内线性带电聚合物的位置。

公开(公告)号：US07405153B2

公开(公告)日：2008-07-29

申请号：US11306932

申请日：2006-01-17

申请人： Sandra G. Malhotra ,  Hariklia Deligianni ,  Stephen M. Rossnagel ,  Xiaoyan Shao ,  Tsong-Lin Tai ,  Oscar van der Straten

发明人： Sandra G. Malhotra ,  Hariklia Deligianni ,  Stephen M. Rossnagel ,  Xiaoyan Shao ,  Tsong-Lin Tai ,  Oscar van der Straten

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28562 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  Y10S438/952

摘要： A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein the second barrier layer is selected from the group consisting of ruthenium, platinum, palladium, rhodium and iridium and wherein the formation of the second barrier layer is manipulated so that the bulk concentration of oxygen in the second barrier layer is 20 atomic percent or less, and forming a conductive layer on the second barrier layer. The process may additionally include a step of treating the second barrier to reduce the amount of oxide on the surface of the second barrier layer.

摘要翻译： 一种在半导体结构中形成互连的方法，包括以下步骤：在衬底上形成电介质层，在电介质层上形成第一阻挡层，在第一阻挡层上形成第二阻挡层，其中第二阻挡层 选自钌，铂，钯，铑和铱，并且其中操作第二阻挡层的形成，使得第二阻挡层中的氧的体积浓度为20原子％以下，并且形成导电 层在第二阻挡层上。 该方法可以另外包括处理第二阻挡层以减少第二阻挡层表面上的氧化物的量的步骤。

公开(公告)号：US20080164613A1

公开(公告)日：2008-07-10

申请号：US11621709

申请日：2007-01-10

申请人： Daniel C. Edelstein ,  Stephen M. Rossnagel

发明人： Daniel C. Edelstein ,  Stephen M. Rossnagel

IPC分类号： H01L23/48 ,  H01L21/288

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper interconnection structure which is electroplated onto a silicon layer or semiconductor substrate. The structure includes an ultra-thin copper seed alloy incorporating selectively minor amounts of a dopant material to facilitate a continuous deposition thereof onto the silicon layer or semiconductor substrate. The copper seed alloy may contain dopant material selected from the group of materials consisting of Ru, Ir, Pt, Pd and alloys thereof. Furthermore, there is provided a method for producing the structure.

摘要翻译： 电镀在硅层或半导体衬底上的铜互连结构。 该结构包括超薄铜种子合金，其选择性地少量掺杂材料，以促进其连续沉积到硅层或半导体衬底上。 铜种子合金可以含有选自由Ru，Ir，Pt，Pd及其合金组成的材料组的掺杂剂材料。 此外，提供了一种制造该结构的方法。

公开(公告)号：US07247946B2

公开(公告)日：2007-07-24

申请号：US11037970

申请日：2005-01-18

申请人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

发明人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

摘要翻译： 公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。 涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。 此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。 选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。 这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

公开(公告)号：US08641879B2

公开(公告)日：2014-02-04

申请号：US13611662

申请日：2012-09-12

申请人： Stefan Harrer ,  Binquan Luan ,  Glenn J. Martyna ,  Hongbo Peng ,  Stanislav Polonsky ,  Stephen M. Rossnagel ,  Ajay K. Royyuru ,  Gustavo A. Stolovitzky ,  George F. Walker

发明人： Stefan Harrer ,  Binquan Luan ,  Glenn J. Martyna ,  Hongbo Peng ,  Stanislav Polonsky ,  Stephen M. Rossnagel ,  Ajay K. Royyuru ,  Gustavo A. Stolovitzky ,  George F. Walker

IPC分类号： G01N27/26

CPC分类号： B82Y15/00 ,  C12Q1/6869 ,  C12Q2565/631

摘要： A technique for controlling the motion of one or more charged entities linked to a polymer through a nanochannel is provided. A first reservoir and a second reservoir are connected by the nanochannel. An array of electrodes is positioned along the nanochannel, where fluid fills the first reservoir, the second reservoir, and the nanochannel. A first electrode is in the first reservoir and a second electrode is in the second reservoir. The first and second electrodes are configured to direct the one or more charged entities linked to the polymer into the nanochannel. An array of electrodes is configured to trap the one or more charged entities in the nanochannel responsive to being controlled for trapping. The array of electrodes is configured to move the one or more charged entities along the nanochannel responsive to being controlled for moving.

公开(公告)号：US08390987B2

公开(公告)日：2013-03-05

申请号：US13559095

申请日：2012-07-26

申请人： Richard A. Haight ,  Stephen M. Rossnagel

发明人： Richard A. Haight ,  Stephen M. Rossnagel

IPC分类号： H01G9/00

CPC分类号： H01G9/145 ,  B82Y99/00 ,  H01G9/004 ,  H01G9/155 ,  Y02E60/13

摘要： A capacitor includes a plurality of nanochannels formed in a dielectric material. A conductive film is formed over interior surfaces of the nanochannels, and a charge barrier is formed over the conductive film. An electrolytic solution is disposed in the nanochannels. An electrode is coupled to the electrolytic solution in the nanochannels to form the capacitor.

摘要翻译： 电容器包括形成在电介质材料中的多个纳米通道。 在纳米通道的内表面上形成导电膜，并且在导电膜上形成电荷势垒。 在纳米通道中设置电解液。 电极与纳米通道中的电解液结合形成电容器。