公开(公告)号：US07846789B2

公开(公告)日：2010-12-07

申请号：US11873205

申请日：2007-10-16

申请人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

发明人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

IPC分类号： H01L21/8238

CPC分类号： H01L21/8249 ,  H01L21/76232 ,  H01L27/0623

摘要： A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.

摘要翻译： 一种半导体器件，包括半导体衬底上或半导体衬底中的第一晶体管器件和衬底上或衬底中的第二晶体管器件。 该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽。 绝缘沟槽的至少一个上角是衬底的横向平面中的圆角。

公开(公告)号：US20090159968A1

公开(公告)日：2009-06-25

申请号：US11960432

申请日：2007-12-19

申请人： Steve L. Merchant ,  John Lin ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Steve L. Merchant ,  John Lin ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823481 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed.

摘要翻译： 双扩散MOS（DMOS）晶体管具有扩展的漏极区域，以提供耗尽区域，其将高漏极电压降低到栅极边缘处的较低电压。 由于与DMOS晶体管并联存在的寄生双极晶体管的回跳，DMOS晶体管在导通状态下的漏极击穿电位低于截止状态下的漏极击穿电位。 本发明是在DMOS源节点上结合有NMOS晶体管的集成电路中的级联DMOS晶体管，以在接通状态操作期间反向偏置寄生发射极 - 基极结，从而消除了快速恢复。 NMOS晶体管可以通过集成电路的互连系统中的连接与DMOS晶体管集成，或者NMOS晶体管和DMOS晶体管可以制造在共同的p型阱中并集成在IC衬底中。 还公开了使用激励级联DMOS晶体管制造集成电路的方法。

公开(公告)号：US07345343B2

公开(公告)日：2008-03-18

申请号：US11195283

申请日：2005-08-02

申请人： Tony T. Phan ,  William C. Loftin ,  John Lin ,  Philip L. Hower

发明人： Tony T. Phan ,  William C. Loftin ,  John Lin ,  Philip L. Hower

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76838

摘要： The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

摘要翻译： 因此，本发明提供一种集成电路及其制造方法。 在一个实施例中，集成电路（100,1000）没有限制地包括位于晶片衬底（110,1010）之上的电介质层（120,1020），以及位于介电层上的半导体衬底（130,1030） 120,120），具有位于其中或其上的一个或多个晶体管器件（140,1040）的半导体衬底（130,1030）。 集成电路（100,1000）还可以包括完全延伸穿过半导体衬底（130,1030）和介电层（120,1020）的互连（170,1053），从而与晶片衬底（110,1010）电接触， 。

公开(公告)号：US07187034B2

公开(公告)日：2007-03-06

申请号：US10888776

申请日：2004-07-09

申请人： Philip L. Hower ,  John Lin ,  Sameer P. Pendharkar ,  Steven L. Merchant

发明人： Philip L. Hower ,  John Lin ,  Sameer P. Pendharkar ,  Steven L. Merchant

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

摘要翻译： 公开了分段功率晶体管和制造方法，其中晶体管段彼此间隔开以促进热扩散，并且其中可以在晶体管段之间的空间中形成其它电气器件。

公开(公告)号：US06958515B2

公开(公告)日：2005-10-25

申请号：US10036323

申请日：2001-12-31

申请人： Philip L. Hower ,  Taylor R. Efland

发明人： Philip L. Hower ,  Taylor R. Efland

IPC分类号： H01L27/085 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66689

摘要： An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.

摘要翻译： 改进的n沟道集成横向DMOS（10），其中在源极（18）下方并自对准并且正常体扩散的掩埋体区域（30）为漏极区域处发射的空穴提供低阻抗路径（ 16）。 这大大减少了二次电子产生，从而降低了寄生PNP双极器件的增益。 减少的再生反过来提高了临界场值，从而提高了安全操作面积。

公开(公告)号：US06815276B2

公开(公告)日：2004-11-09

申请号：US10264038

申请日：2002-10-03

申请人： Philip L. Hower ,  John Lin ,  Sameer P. Pendharkar ,  Steven L. Merchant

发明人： Philip L. Hower ,  John Lin ,  Sameer P. Pendharkar ,  Steven L. Merchant

IPC分类号： H01L21336

CPC分类号： H01L29/7816 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

摘要翻译： 公开了分段功率晶体管和制造方法，其中晶体管段彼此间隔开以促进热扩散，并且其中可以在晶体管段之间的空间中形成其它电气器件。

公开(公告)号：US5164813A

公开(公告)日：1992-11-17

申请号：US700107

申请日：1991-05-08

申请人： Scott C. Blackstone ,  Philip L. Hower ,  Elizabeth M. Roughan ,  Christopher H. Doucette ,  Roy Lee ,  Carolyn Q. Cotnam

发明人： Scott C. Blackstone ,  Philip L. Hower ,  Elizabeth M. Roughan ,  Christopher H. Doucette ,  Roy Lee ,  Carolyn Q. Cotnam

IPC分类号： H01L21/18 ,  H01L21/329 ,  H01L23/051 ,  H01L29/861

CPC分类号： H01L29/66113 ,  H01L21/187 ,  H01L23/051 ,  H01L24/01 ,  H01L29/861 ,  H01L29/8613 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12043

摘要： A new diode structure is provided by bonding two semiconductor materials together having a low capacitance, a large contact area and mechanical ruggedness. The cross-sectional area of at least one of the semiconductor materials is reduced in the region of the bond resulting in a structure with either an hourglass or truncated hourglass-like cross-section. A diode PN junction is contained in the neighborhood of the area of reduced cross section. The diode so constructed provides a sufficient spacing between the unbonded semiconductor regions to reduce total packaged diode capacitance without introducing a spacer layer. The diode is processed to limit the area of the PN junction formed therein to the region of the bonding between the semiconductor materials, without limiting the metallized contact area, further controlling the diode capacitance as well as other electrical characteristics. The outer ends of the diode parallel to the bond, comprising typically P and N type semiconductor regions, are typically connected to metal leads which comprise the diode leads and the diode is packaged to form a mechanically and electrically stable low capacitance diode. This diode can be encapsulated such that no void or cavity exists within the interior of the structure without changing the diode construction process.

摘要翻译： 通过将两个半导体材料结合在一起，具有低电容，大的接触面积和机械坚固性来提供新的二极管结构。 至少一种半导体材料的横截面面积在结合区域中减小，从而产生具有沙漏或截短的沙漏状横截面的结构。 二极管PN结包含在减小截面的区域附近。 如此构造的二极管在未连接的半导体区域之间提供足够的间隔，以减少总封装的二极管电容而不引入间隔层。 处理二极管以限制形成在其中的PN结的区域到半导体材料之间的接合区域，而不限制金属化接触面积，进一步控制二极管电容以及其它电特性。 平行于键合的二极管的外端，通常包括P型和N型半导体区，通常连接到包括二极管引线的金属引线，并且二极管被封装以形成机械和电气稳定的低电容二极管。 该二极管可以被封装成使得在结构内部不存在空隙或空腔而不改变二极管构造过程。

公开(公告)号：US4901120A

公开(公告)日：1990-02-13

申请号：US61189

申请日：1987-06-10

申请人： Carson E. Weaver ,  Philip L. Hower

发明人： Carson E. Weaver ,  Philip L. Hower

IPC分类号： H01L29/73 ,  H01L29/861 ,  H01L29/872

CPC分类号： H01L29/8611 ,  H01L29/7302 ,  H01L29/872

摘要： A bipolar junction structure comprising a Schottky barrier rectifying contact juxtaposed to a p-n junction having the distribution of p+ diffusions common to a guard ring structure on the Schottky barrier area.

摘要翻译： 一种双极结结构，包括与肖特基势垒区上的保护环结构共有的p +扩散分布的p-n结并置的肖特基势垒整流触点。

公开(公告)号：US4231059A

公开(公告)日：1980-10-28

申请号：US956813

申请日：1978-11-01

申请人： Philip L. Hower ,  Derrick J. Page

发明人： Philip L. Hower ,  Derrick J. Page

IPC分类号： H01L29/41 ,  H01L21/331 ,  H01L23/48 ,  H01L23/482 ,  H01L29/417 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/4824 ,  H01L24/72 ,  H01L29/41708 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/19043

摘要： A transistor in which this effective emitter resistance which is determined by the geometry of the emitter metallization as disclosed. In the preferred embodiment, the emitter metallization comprises a series of circular "dots" which are distributed over the entire emitter area. The area of the "dots" with respect to the entire emitter area is selected such that the desired effective emitter resistance is achieved.

摘要翻译： 其中这种有效发射极电阻由发射体金属化的几何形状确定的晶体管，如所公开的。 在优选实施例中，发射极金属化包括分布在整个发射极区域上的一系列圆形“点”。 选择相对于整个发射极区域的“点”的面积，使得实现期望的有效发射极电阻。

公开(公告)号：US4112362A

公开(公告)日：1978-09-05

申请号：US755619

申请日：1976-12-30

申请人： Philip L. Hower ,  William G. Carlson ,  Tapan K. Gupta

发明人： Philip L. Hower ,  William G. Carlson ,  Tapan K. Gupta

IPC分类号： G01R31/12 ,  G01R15/00 ,  G01R31/00 ,  G01R31/16 ,  G01R31/02

CPC分类号： G01R31/00 ,  G01R15/00

摘要： A method for the nondestructive testing of voltage limiting blocks includes the steps of providing several discrete electrical contacts across the block, sequentially applying to each of the contacts a voltage to determine the corresponding current and utilizing the current and voltage values to determine constants related to the microstructure of that particular location. The constants can then be utilized to derive a contour map which will be indicative of a hot spot in such block as determined by a maxima of the contour map.

摘要翻译： 用于电压限制块的非破坏性测试的方法包括以下步骤：在块上提供几个离散的电触点，顺序地向每个触点施加电压以确定相应的电流并利用电流和电压值来确定与 该特定位置的微观结构。 然后可以使用常数来导出轮廓图，其将指示由等高线图的最大值确定的这种块中的热点。