公开(公告)号：US20070085579A1

公开(公告)日：2007-04-19

申请号：US11551150

申请日：2006-10-19

申请人： John Wallberg ,  Robert Staszewski

发明人： John Wallberg ,  Robert Staszewski

IPC分类号： H03L7/06 ,  H03D3/24

CPC分类号： H03L7/08 ,  H03L2207/50

摘要： A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

摘要翻译： 一种新颖的机理，用于使用频率检测器观察和比较参考和可变PLL环路信号的微分相位。 然后累积产生的相位微分误差以产生相位误差。 与频率检测器的环路的操作在数学上等同于相位检测器。 频率误差累加器用于产生频率误差的积分。 频率误差累加器还能够在检测到足够大的扰动时停止频率的累积，从而有效地冻结环路的操作，因为随后的频率误差更新不被累积。 在去除相位冻结事件时，恢复频率误差的累积，从而恢复正常循环操作。

公开(公告)号：US20060164160A1

公开(公告)日：2006-07-27

申请号：US11388558

申请日：2006-03-24

申请人： Khurram Muhammad ,  Robert Staszewski ,  Dirk Leipold

发明人： Khurram Muhammad ,  Robert Staszewski ,  Dirk Leipold

IPC分类号： H03K5/00

CPC分类号： H04B1/109 ,  H03H19/004

摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.

摘要翻译： 改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。 该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

公开(公告)号：US20060038710A1

公开(公告)日：2006-02-23

申请号：US11203019

申请日：2005-08-11

申请人： Robert Staszewski ,  Oren Eliezer

发明人： Robert Staszewski ,  Oren Eliezer

IPC分类号： H03M3/00

CPC分类号： H03F3/24 ,  H03F2200/331 ,  H03M1/005 ,  H03M1/68 ,  H03M1/747 ,  H03M3/50 ,  H03M7/3022 ,  H04L27/361

摘要： A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

公开(公告)号：US20070085623A1

公开(公告)日：2007-04-19

申请号：US11550957

申请日：2006-10-19

申请人： Robert Staszewski ,  John Wallberg

发明人： Robert Staszewski ,  John Wallberg

IPC分类号： H03L5/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L7/1806 ,  H03L2207/50 ,  H04L27/361 ,  H04L27/368

摘要： A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.

摘要翻译： 一种用于在基于全数字锁相环（ADPLL）的数字控制振荡器（DCO）中增益归一化的新颖机制，其可操作地在调制路径和PLL环路之间分离增益归一化乘法功能。 调制环路（称为调制路径乘法器）的增益归一化包括全位分辨率高精度乘法函数。 另一方面，PLL环路的增益归一化具有显着更低的分辨率，因此需要较低复杂度的乘法器逻辑电路。

公开(公告)号：US20060291589A1

公开(公告)日：2006-12-28

申请号：US11203504

申请日：2005-08-11

申请人： Oren Eliezer ,  Francis Cruise ,  Robert Staszewski ,  Jaimin Mehta

发明人： Oren Eliezer ,  Francis Cruise ,  Robert Staszewski ,  Jaimin Mehta

IPC分类号： H04L27/12

CPC分类号： H03F3/24 ,  H03C3/40 ,  H03C5/00 ,  H03F2200/324 ,  H03F2200/331 ,  H03F2200/336 ,  H04K1/02 ,  H04L27/04 ,  H04L27/2092 ,  H04L27/365

摘要： A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

摘要翻译： 一种用于复调制器的全数字正交架构的新型装置和方法。 复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标（r，θ）的那些。 调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号 。 相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。 提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。

公开(公告)号：US20060135107A1

公开(公告)日：2006-06-22

申请号：US11339386

申请日：2006-01-25

申请人： Robert Staszewski ,  Khurram Muhammad ,  Dirk Leipold

发明人： Robert Staszewski ,  Khurram Muhammad ,  Dirk Leipold

IPC分类号： H04B1/10

CPC分类号： H04B1/28 ,  H04B1/1036

摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.

摘要翻译： 通过反馈消除接近干扰的系统和方法。 优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。 干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。 然后在采样单元中消除干扰源。 另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

公开(公告)号：US20060038624A1

公开(公告)日：2006-02-23

申请号：US10924220

申请日：2004-08-23

申请人： Chih-Ming Hung ,  Robert Staszewski ,  Dirk Leipol

发明人： Chih-Ming Hung ,  Robert Staszewski ,  Dirk Leipol

IPC分类号： H03B5/12 ,  H03K3/282

CPC分类号： H03B5/08

摘要： An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.

摘要翻译： 一种用于提供谐振信号的第n / O级振荡器系统，产生谐振信号的方法和通信系统。 在一个实施例中，n大于2的n阶振荡器系统包括（1）被配置为提供中间信号的放大器和（2）包括n + 并且被配置为通过将中间信号的复数滤波形式反馈到放大器来产生谐振信号。

公开(公告)号：US20060033582A1

公开(公告)日：2006-02-16

申请号：US11149859

申请日：2005-06-10

申请人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

发明人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

IPC分类号： H03L7/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L2207/50

摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

摘要翻译： 一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。 增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。 然后将梯度缩放并添加到DCO增益乘数的当前值。

公开(公告)号：US20050264333A1

公开(公告)日：2005-12-01

申请号：US11195060

申请日：2005-08-02

申请人： Robert Staszewski ,  Dirk Leipold ,  Kenneth Maggio

发明人： Robert Staszewski ,  Dirk Leipold ,  Kenneth Maggio

IPC分类号： H03F1/02 ,  H03F1/06 ,  H03F3/217 ,  H03K3/00 ,  H03K3/017 ,  H03K5/06 ,  H03K7/02 ,  H04B1/04

CPC分类号： H03F1/02 ,  H03F1/0205 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2176 ,  H03F2200/331 ,  H03K5/06 ,  H03K7/02 ,  H04B1/0483 ,  H04B2001/0491

摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

公开(公告)号：US20050233725A1

公开(公告)日：2005-10-20

申请号：US10828386

申请日：2004-04-20

申请人： Khurram Muhammad ,  Robert Staszewski ,  Dirk Leipold

发明人： Khurram Muhammad ,  Robert Staszewski ,  Dirk Leipold

IPC分类号： H03D7/18 ,  H03H19/00 ,  H04B1/16 ,  H04B1/28

CPC分类号： H03D7/18 ,  H03H19/004 ,  H03H2007/0192

摘要： Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.

摘要翻译： 公开了用于IF或RF系统的多抽头直接采样混频器（MTDSM）中的图像抑制滤波的方法，电路和系统。 公开了在信号处理系统的同相和正交分支中使用旋转电容器。 在I和Q通道的分支之间的信息交换被用于实现复杂的过滤器。 还公开了使用复合滤波器的级联多级以提供更高阶复数滤波器的实施例。