公开(公告)号：US20060291589A1

公开(公告)日：2006-12-28

申请号：US11203504

申请日：2005-08-11

申请人： Oren Eliezer ,  Francis Cruise ,  Robert Staszewski ,  Jaimin Mehta

发明人： Oren Eliezer ,  Francis Cruise ,  Robert Staszewski ,  Jaimin Mehta

IPC分类号： H04L27/12

CPC分类号： H03F3/24 ,  H03C3/40 ,  H03C5/00 ,  H03F2200/324 ,  H03F2200/331 ,  H03F2200/336 ,  H04K1/02 ,  H04L27/04 ,  H04L27/2092 ,  H04L27/365

摘要： A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

摘要翻译： 一种用于复调制器的全数字正交架构的新型装置和方法。 复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标（r，θ）的那些。 调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号 。 相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。 提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。

公开(公告)号：US20070103240A1

公开(公告)日：2007-05-10

申请号：US11619529

申请日：2007-01-03

申请人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

发明人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

IPC分类号： H03L7/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L2207/50

摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

摘要翻译： 一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。 增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。 然后将梯度缩放并添加到DCO增益乘数的当前值。

公开(公告)号：US20060132431A1

公开(公告)日：2006-06-22

申请号：US11015562

申请日：2004-12-17

申请人： Oren Eliezer ,  Carl Panasik ,  John Wallberg ,  Robert Staszewski

发明人： Oren Eliezer ,  Carl Panasik ,  John Wallberg ,  Robert Staszewski

IPC分类号： G09G5/00

CPC分类号： G06F3/0317 ,  G06F1/1616 ,  G06F1/1626 ,  G06F1/1684 ,  G06F1/1686 ,  G06F1/169 ,  G06F1/1694 ,  G06F1/1698 ,  G06F3/0354 ,  G06F3/03547 ,  G06F3/04886 ,  H04M2250/52 ,  H04W52/0267 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/23

摘要： System and method for interfacing with a digital computer using a multi-function device. A preferred embodiment comprises a multi-function device comprising a controller configured to process information and regulate operations of the multi-function device, a sensor coupled to the controller, the sensor configured to capture information in a movement of the multi-function device or a movement of an object applied to the multi-function device and to provide the information to the controller, wherein the information is used to determine movement information. The multi-function device further comprises a radio frequency circuit also coupled to the controller, the radio frequency circuit is configured to exchange information with other devices via a plurality of communications networks, wherein one of the other devices is a computer and the information shared is movement information from the multi-function device.

摘要翻译： 使用多功能设备与数字计算机进行接口的系统和方法。 优选实施例包括多功能设备，其包括被配置为处理信息并调节多功能设备的操作的控制器，耦合到控制器的传感器，被配置为捕获多功能设备的移动中的信息或 应用于多功能装置的物体的移动以及将信息提供给控制器，其中所述信息用于确定移动信息。 多功能设备还包括还耦合到控制器的射频电路，射频电路被配置为经由多个通信网络与其他设备交换信息，其中其他设备之一是计算机，并且共享的信息是 来自多功能设备的运动信息。

公开(公告)号：US20060038710A1

公开(公告)日：2006-02-23

申请号：US11203019

申请日：2005-08-11

申请人： Robert Staszewski ,  Oren Eliezer

发明人： Robert Staszewski ,  Oren Eliezer

IPC分类号： H03M3/00

CPC分类号： H03F3/24 ,  H03F2200/331 ,  H03M1/005 ,  H03M1/68 ,  H03M1/747 ,  H03M3/50 ,  H03M7/3022 ,  H04L27/361

摘要： A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

公开(公告)号：US20060119493A1

公开(公告)日：2006-06-08

申请号：US11297524

申请日：2005-12-07

申请人： Nir Tal ,  Sameh Rezeg ,  Robert Staszewski ,  Oren Eliezer ,  Ofer Friedman

发明人： Nir Tal ,  Sameh Rezeg ,  Robert Staszewski ,  Oren Eliezer ,  Ofer Friedman

IPC分类号： H03M3/00

CPC分类号： H03M7/3017 ,  H03M7/3022 ,  H03M7/3042

摘要： A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

摘要翻译： 一种采用具有噪声传递函数的Σ-Δ调制器的发射机，其适于在至少一个感兴趣的频带之外移位量化噪声。 提出了一种用于合成单环Σ-Δ调制器中的控制器的技术，使得噪声传递函数可以从满足某些条件的函数族中任意选择。 使用新颖的调制器设计技术，支持极坐标和笛卡尔（即正交）发射机结构。 呈现采用极性发射调制的发射机，其对数字控制的功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。 类似地，呈现采用笛卡尔发射调制的发射机，其对混合功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。

公开(公告)号：US20060033582A1

公开(公告)日：2006-02-16

申请号：US11149859

申请日：2005-06-10

申请人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

发明人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

IPC分类号： H03L7/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L2207/50

摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

摘要翻译： 一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。 增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。 然后将梯度缩放并添加到DCO增益乘数的当前值。

公开(公告)号：US20050287967A1

公开(公告)日：2005-12-29

申请号：US11115815

申请日：2005-04-26

申请人： Chih-Ming Hung ,  Francis Cruise ,  Dirk Leipold ,  Robert Staszewski

发明人： Chih-Ming Hung ,  Francis Cruise ,  Dirk Leipold ,  Robert Staszewski

IPC分类号： H01Q11/12 ,  H03F1/32 ,  H03F3/191 ,  H04B1/04

CPC分类号： H04B1/0483 ,  H03F1/3241 ,  H03F1/3294 ,  H03F3/191 ,  H03F2200/331

摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.

摘要翻译： 一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。 首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

公开(公告)号：US20060290435A1

公开(公告)日：2006-12-28

申请号：US11464420

申请日：2006-08-14

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

IPC分类号： H03L7/00

CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

公开(公告)号：US20060256910A1

公开(公告)日：2006-11-16

申请号：US11382570

申请日：2006-05-10

申请人： Nir Tal ,  Robert Staszewski ,  Ofer Friedman

发明人： Nir Tal ,  Robert Staszewski ,  Ofer Friedman

IPC分类号： H04B1/00 ,  H03D3/24 ,  H04B1/713

CPC分类号： H04B1/7136 ,  H03C3/40 ,  H03D3/007 ,  H03L7/08 ,  H03L7/0991 ,  H04B1/71635 ,  H04B1/71637 ,  H04B2001/71365

摘要： A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.

摘要翻译： 一种新颖有用的快速频率合成器和发射机。 频率合成器和发射器包含适用于操作开环的数字控制振荡器（DCO）。 通过改变振荡器调谐字（OTW）来模拟UWB发射机的三个振荡器来实现瞬时频率切换。 在一个实施例中，DCO可以在用于构造DCO的变容二极管装置的1 / f T T中瞬时改变频率。 在数据包发送或接收开始之前，全数字锁相环（ADPLL）用于离线校准。 开关期间的任何相移都由发射机中的数字电路跟踪。 在第二实施例中，通过使用有效地产生有效地移动合成频率的精细分辨率复指数波形的数控振荡器（NCO）来提供额外的频率精度。 混频器在转换为数字域之前将波形应用于I和Q数据采样。

公开(公告)号：US20050212606A1

公开(公告)日：2005-09-29

申请号：US11122670

申请日：2005-05-04

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

IPC分类号： H03F1/02 ,  H03F1/32 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/00

CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。