公开(公告)号：US10298381B1

公开(公告)日：2019-05-21

申请号：US15967434

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  Shih-Wei Chou ,  Ying Duan

IPC: H04L7/00

Abstract: Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.

公开(公告)号：US20190065431A1

公开(公告)日：2019-02-28

申请号：US16056885

申请日：2018-08-07

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Chulkyu Lee ,  Harvijaysinh Raj

IPC: G06F13/42 ,  G06F3/16 ,  G06F1/12

Abstract: Providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses is disclosed. In one aspect, a downstream-facing interface (DFI) device determines a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern, and adjusts the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. The processor-based DFI device then transmits the bitstream containing the next synchronization strobe (e.g., via a SOUNDWIRE Extension bus, such as a SOUNDWIRE-XL or SOUNDWIRE-NEXT bus, to one or more upstream-facing interface (UFI) devices). In another aspect, a processor-based UFI device receives the bitstream, and detects the encoded polarity of the synchronization strobe. The processor-based UFI device reconstructs the frame synchronization pattern based on the polarity of the synchronization strobe, and performs frame synchronization based on the frame synchronization pattern.

公开(公告)号：US20180358939A1

公开(公告)日：2018-12-13

申请号：US15912170

申请日：2018-03-05

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  Shih-Wei Chou ,  Ying Duan

IPC: H03F3/217 ,  H03F1/02

CPC classification number: H03F3/2178 ,  H03F1/0244 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45197 ,  H04B1/06

Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor

公开(公告)号：US09998154B2

公开(公告)日：2018-06-12

申请号：US15172913

申请日：2016-06-03

Applicant: QUALCOMM Incorporated

Inventor： Shih-Wei Chou ,  Chulkyu Lee ,  Dhaval Sejpal

IPC: H04B1/04 ,  H04B3/52 ,  G06F13/40 ,  H04L25/02 ,  H04L25/493

CPC classification number: H04B1/04 ,  G06F13/4072 ,  H04B3/52 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/493

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.

公开(公告)号：US09961174B2

公开(公告)日：2018-05-01

申请号：US14156329

申请日：2014-01-15

Applicant: QUALCOMM Incorporated

Inventor： Xiang Li ,  Nakul Midha ,  Varun Radhakrishnan ,  Chulkyu Lee

IPC: H04M17/00 ,  H04M1/02 ,  H04B17/00 ,  H04L25/02 ,  H04L25/49 ,  G01R31/28

CPC classification number: H04M1/0266 ,  G01R31/2848 ,  H04B17/00 ,  H04L25/0272 ,  H04L25/4917

Abstract: System, methods and apparatus are described that model analog behavior in a multi-wire, multi-phase communications link. A digital signal representative of a physical connection in a communications link and a virtual signal characterizing a three-phase signal transmitted over the physical connection are generated. The virtual signal may be configured to model one or more analog characteristics of the physical connection. The analog characteristics may include voltage states defining the three-phase signal. The analog characteristics of the physical connection include at least three voltage states corresponding to signaling states of the three-phase signal.

公开(公告)号：US09842073B2

公开(公告)日：2017-12-12

申请号：US15041901

申请日：2016-02-11

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley

IPC: H04L7/00 ,  G06F13/36 ,  G06F13/42 ,  H04L25/49 ,  G06F13/40

CPC classification number: G06F13/36 ,  G06F13/4063 ,  G06F13/4068 ,  G06F13/4278 ,  G06F13/4282 ,  H04L7/0033 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/4919 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

公开(公告)号：US20170026083A1

公开(公告)日：2017-01-26

申请号：US14808272

申请日：2015-07-24

Applicant: QUALCOMM Incorporated

Inventor： Dhaval Sejpal ,  Chulkyu Lee ,  George Alan Wiley

IPC: H04B3/54 ,  H04B3/462

CPC classification number: H04B3/54 ,  H04B3/462 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0286 ,  H04L25/14 ,  H04L25/4917

Abstract: A method, an apparatus, and a computer program product for data communication over a multi-wire, multi-phase interface are provided. The method may include providing a sequence of symbols to be transmitted on a 3-wire interface, each symbol in the sequence of symbols defining one of three voltage states for each wire of the 3-wire interface, driving all wires of the 3-wire interface to a common voltage state during a transition from a first transmitted symbol to a second transmitted symbol, driving each wire of the 3-wire interface in accordance with the second transmitted symbol after a predetermined delay. Each wire may be in a different voltage state from the other wires of the 3-wire interface during transmission of the each symbol. The common voltage state may lie between two of the three voltage states.

Abstract translation: 提供了一种用于通过多线，多相接口进行数据通信的方法，装置和计算机程序产品。 该方法可以包括提供要在3线接口上发送的符号序列，符号序列中的每个符号定义3线接口的每根线的三种电压状态之一，驱动3线的所有线 在从第一传输符号到第二传输符号的转变期间接合到公共电压状态，在预定延迟之后根据第二传输符号驱动3线接口的每条线。 在每个符号的传输期间，每根导线可能处于与3线接口的其它线不同的电压状态。 公共电压状态可以位于三个电压状态中的两个之间。

公开(公告)号：US20160127121A1

公开(公告)日：2016-05-05

申请号：US14992450

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L7/027 ,  H04L25/493 ,  H04L25/02

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential number from a set of sequential numbers. The sequential number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换号码都从一组连续号码转换为一个顺序号码。 顺序号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播分散在多条n线上，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为序列号可保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零差分电压。

公开(公告)号：US09319218B2

公开(公告)日：2016-04-19

申请号：US14315142

申请日：2014-06-25

Applicant: QUALCOMM Incorporated

Inventor： Shree Krishna Pandey ,  Arun Chandra Kundu ,  George Alan Wiley ,  Chulkyu Lee

IPC: H04L25/02 ,  H04L7/00 ,  H04B3/00 ,  H04B3/462 ,  H04B3/54

CPC classification number: H04L7/0041 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L25/0264

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

公开(公告)号：US20160099817A1

公开(公告)日：2016-04-07

申请号：US14966236

申请日：2015-12-11

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Glenn Raskin ,  Chulkyu Lee

IPC: H04L25/02 ,  H04L25/49 ,  H04L5/20

CPC classification number: H04L25/0272 ,  H04L5/20 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L25/4917

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 数据以多位符号编码，并且多位符号在多个连接器上传输。 可以通过将符号映射到多个连接器的状态序列来传输多比特符号，并且根据状态序列来驱动连接器。 状态序列的定时可以在连续状态之间的每个转换处在接收器处确定。 每个连接器的状态可以由在每个连接器上传输的多相信号的极性和旋转方向来定义。