公开(公告)号：US20150186279A1

公开(公告)日：2015-07-02

申请号：US14146576

申请日：2014-01-02

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Jungwon Suh

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F3/0608 ,  G06F12/0873 ,  G06F12/0895 ,  G06F12/12 ,  G06F2206/1004 ,  Y02D10/13

Abstract: A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

Abstract translation: 公开了一种用于对存储器进行碎片整理的系统和方法。 在特定实施例中，一种方法包括将存储在存储器的第一物理存储器地址上的数据从存储器加载到数据高速缓存的高速缓存行中。 第一个物理内存地址映射到第一个虚拟内存地址。 该方法还包括在数据高速缓存处启动与第一虚拟存储器地址相关联的查找信息的修改，使得第一虚拟存储器地址对应于存储器的第二物理存储器地址。 该方法还包括在数据高速缓存处修改与高速缓存行相关联的信息，以指示高速缓存线对应于第二物理存储器地址而不是第一物理存储器地址。

公开(公告)号：US20150149865A1

公开(公告)日：2015-05-28

申请号：US14090427

申请日：2013-11-26

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Jungwon Suh

IPC: G06F11/10

CPC classification number: G06F11/1064 ,  G06F12/00

Abstract: A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache.

Abstract translation: 响应于确定数据是干净的，一种方法包括生成与要存储在高速缓存中的数据相关联的错误检测信息。 该方法还包括将清洁数据存储在高速缓存的第一区域。 响应于确定数据是脏的，该方法还包括生成与要存储在高速缓存中的数据相关联的纠错信息。 该方法还包括将脏数据存储在高速缓存的第二区域。

公开(公告)号：US20140201435A1

公开(公告)日：2014-07-17

申请号：US13743400

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Xiangyu Dong ,  Jungwon Suh

IPC: G11C11/406 ,  G06F12/08

CPC classification number: G11C11/40603 ,  G06F12/08 ,  G06F13/1694 ,  Y02D10/14

Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

Abstract translation: 公开了用于在基于处理器的系统中支持异构存储器访问请求的异构存储器系统以及相关方法和计算机可读介质。 异构存储器系统由可以针对给定存储器访问请求访问的多个均匀存储器组成。 每个均匀存储器具有特定的功率和性能特性。 在这方面，存储器访问请求可以有利地基于存储器访问请求以及功率和/或性能考虑路由到异构存储器系统中的同构存储器之一。 作为非限制性示例，异类存储器访问请求策略可以基于诸如读/写类型，页面命中的频率和存储器流量的关键操作参数动态地预定义或确定。 以这种方式，存储器访问请求时间可以被优化以被减少，而不需要进行与仅具有可用于存储的一个存储器类型相关联的权衡。

公开(公告)号：US12153531B2

公开(公告)日：2024-11-26

申请号：US18059937

申请日：2022-11-29

Applicant: QUALCOMM Incorporated

Inventor： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F13/16

Abstract: This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

公开(公告)号：US11893240B2

公开(公告)日：2024-02-06

申请号：US17452606

申请日：2021-10-28

Applicant: QUALCOMM Incorporated

Inventor： Shyamkumar Thoziyoor ,  Pankaj Deshmukh ,  Jungwon Suh ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0635 ,  G06F3/0679

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

公开(公告)号：US11728003B2

公开(公告)日：2023-08-15

申请号：US17245981

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/1045 ,  G11C29/18 ,  G11C29/44 ,  G11C2029/1202

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US11662919B2

公开(公告)日：2023-05-30

申请号：US17494089

申请日：2021-10-05

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

IPC: G06F3/06 ,  G06F12/0875

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0875 ,  G06F2212/1028 ,  G06F2212/45

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US11164618B2

公开(公告)日：2021-11-02

申请号：US16907103

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C5/00 ,  G11C11/406 ,  G11C7/10 ,  G11C8/12

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US20190179399A1

公开(公告)日：2019-06-13

申请号：US16268634

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo

IPC: G06F1/3234 ,  G06F13/42 ,  G06F12/06 ,  G11C7/10 ,  G06F13/16 ,  G06F1/3225

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

公开(公告)号：US09633698B2

公开(公告)日：2017-04-25

申请号：US14280313

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Vaishnav Srinivas ,  David Ian West ,  Deepti Vijayalakshmi Sriramagiri ,  Jungwon Suh ,  Jason Thurston

IPC: G06F11/00 ,  G11C5/14 ,  G06F11/07 ,  G06F11/10 ,  G01R31/317

CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.