公开(公告)号：US11290109B1

公开(公告)日：2022-03-29

申请号：US17030087

申请日：2020-09-23

Applicant: QUALCOMM Incorporated

Inventor： Foua Vang ,  Hyeokjin Lim ,  Seung Hyuk Kang ,  Venugopal Boynapalli ,  Shitiz Arora

IPC: H01L21/00 ,  H03K19/094 ,  H01L23/528

Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

公开(公告)号：US11237580B1

公开(公告)日：2022-02-01

申请号：US17015486

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Foua Vang ,  Ramaprasath Vilangudipitchai ,  Seung Hyuk Kang ,  Venugopal Boynapalli

IPC: G05F1/46 ,  H03K19/00 ,  H03K17/22

Abstract: A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.

公开(公告)号：US20180167058A1

公开(公告)日：2018-06-14

申请号：US15372866

申请日：2016-12-08

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H03K3/012 ,  H03K5/135 ,  H03K3/356

CPC classification number: H03K3/356052 ,  G06F1/3237 ,  H03K3/35606 ,  H03K3/356104 ,  H03K3/356156 ,  H03K19/0016

Abstract: According to certain aspects, a method for clock gating includes receiving an enable signal, and latching a logic value of the enable signal on an edge of an input clock signal. The method also includes passing the latched logic value of the enable signal to a clock-gating output when the input clock signal is logically high, blocking the latched logic value of the enable signal from the clock-gating output when the input clock signal is logically low, and pulling the clock-gating output logically low when the input clock signal is logically low.

公开(公告)号：US09979381B1

公开(公告)日：2018-05-22

申请号：US15338181

申请日：2016-10-28

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H03K3/356 ,  H03K3/012 ,  H03K19/20

CPC classification number: H03K3/012 ,  H03K3/356121 ,  H03K3/356156 ,  H03K19/0016 ,  H03K19/20

Abstract: Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.

公开(公告)号：US09666301B2

公开(公告)日：2017-05-30

申请号：US14488171

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G01R31/28 ,  G11C29/08 ,  G11C29/32 ,  G11C8/16 ,  G11C29/20

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

公开(公告)号：US09577639B1

公开(公告)日：2017-02-21

申请号：US14864486

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Bruce Lim ,  Mukul Gupta ,  Hananel Kang ,  Chih-lung Kao ,  Radhika Guttal

IPC: H03K19/0948 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528

CPC classification number: H03K19/0948 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924

Abstract: A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating.

Abstract translation: MOS器件包括具有第一MOS晶体管源极，第一MOS晶体管漏极和第一MOS晶体管栅极的第一MOS晶体管。 MOS器件还包括具有第二MOS晶体管源极，第二MOS晶体管漏极和第二MOS晶体管栅极的第二MOS晶体管。 第二MOS晶体管源和第一MOS晶体管源耦合到第一电压源。 MOS器件包括具有第三MOS晶体管栅极的第三MOS晶体管，第一MOS晶体管源极和第三MOS晶体管源极之间的第三MOS晶体管栅极，第三MOS晶体管还具有第三MOS晶体管源极和第三MOS晶体管漏极 所述第三MOS晶体管源耦合到所述第一MOS晶体管源，所述第三MOS晶体管漏极耦合到所述第二MOS晶体管源，所述第三MOS晶体管栅极浮置。

公开(公告)号：US20170026044A1

公开(公告)日：2017-01-26

申请号：US15289740

申请日：2016-10-10

Applicant: QUALCOMM Incorporated

Inventor： Kevin Robert Bowles ,  Jose Gabriel Corona ,  Venugopal Boynapalli

IPC: H03K19/0185 ,  H03K3/356 ,  H03K17/00

CPC classification number: H03K19/018528 ,  H03K3/35613 ,  H03K17/002 ,  H03K17/005 ,  H03K19/018507

Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.

Abstract translation: 本文描述了用于电平转换复用的系统和方法。 在一个实施例中，一种用于电平转换复用的方法包括：基于一个或多个选择信号选择多个输入中的一个，并且基于所述多个输入中所选择的一个输入的逻辑状态来下拉第一和第二节点中的一个 。 该方法还包括如果第二节点被拉下来则拉起第一节点，并且如果第一节点被拉下来则提起第二节点。

公开(公告)号：US09189438B2

公开(公告)日：2015-11-17

申请号：US13799286

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venugopal Boynapalli ,  Kevin Robert Bowles ,  Vijay Bantval

IPC: G06F13/40

CPC classification number: G06F13/40 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.

Abstract translation: 总线通信架构中的动态功率降低的各个方面在本文中被描述为体现在XBAR架构中，其提供多路径和中继器电路的灵活门控，以允许多个所选择的客户端中的任何一个与任何其他互连的客户端通信，同时减少 通过禁用总线通信架构中的未使用的中继器电路来实现动态功耗。

公开(公告)号：US09081060B2

公开(公告)日：2015-07-14

申请号：US14046084

申请日：2013-10-04

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli ,  Sagar Suresh Sabade ,  Bilal Zafar

IPC: G01R31/3177 ,  G01R31/3185 ,  G06F11/27 ,  G01R31/3187

CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

公开(公告)号：US20140281112A1

公开(公告)日：2014-09-18

申请号：US13799286

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hari Rao ,  Venugopal Boynapalli ,  Kevin Robert Bowles ,  Vijay Bantval

IPC: G06F13/40

CPC classification number: G06F13/40 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.

Abstract translation: 总线通信架构中的动态功率降低的各个方面在本文中被描述为体现在XBAR架构中，其提供多路径和中继器电路的灵活门控，以允许多个所选择的客户端中的任何一个与任何其他互连的客户端通信，同时减少 通过禁用总线通信架构中的未使用的中继器电路来实现动态功耗。