公开(公告)号：US5937319A

公开(公告)日：1999-08-10

申请号：US961828

申请日：1997-10-31

Applicant: Qi Xiang ,  Subash Gupta ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Subash Gupta ,  Ming-Ren Lin

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/336

CPC classification number: H01L21/28123

Abstract: A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the polysilicon gate 8, silicidizing the metal with the polysilicon in the polysilicon gate 8 to form a metal silicide sidewall 20, and removing the metal silicide sidewall 20 by etching.

Abstract translation: 在集成电路中的金属氧化物半导体（MOS）晶体管中制造多晶硅栅极8的方法包括在多晶硅栅极8的侧壁12上提供诸如钴的金属层18，在金属氧化物半导体 多晶硅栅极8以形成金属硅化物侧壁20，并通过蚀刻去除金属硅化物侧壁20。

公开(公告)号：US09460924B2

公开(公告)日：2016-10-04

申请号：US11691332

申请日：2007-03-26

Applicant: Witold P. Maszara ,  Qi Xiang

Inventor： Witold P. Maszara ,  Qi Xiang

IPC: H01L21/00 ,  H01L21/033

CPC classification number: H01L21/0337

Abstract: A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.

Abstract translation: 提供一种用于形成半导体器件的方法，包括处理具有间隔层和结构层的晶片，间隔层在结构层之上。 该方法继续，包括从间隔层形成第一侧壁间隔物，从第一侧壁间隔物下方的结构层形成结构带，在结构带上方形成掩模结构，并与结构带相交并形成从结构带下方的垂直柱 掩蔽结构。

公开(公告)号：US09196749B1

公开(公告)日：2015-11-24

申请号：US13341310

申请日：2011-12-30

Applicant: Charu Sardana ,  Albert Ratnakumar ,  Qi Xiang ,  Bradley Jensen

Inventor： Charu Sardana ,  Albert Ratnakumar ,  Qi Xiang ,  Bradley Jensen

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/112

CPC classification number: H01L27/112 ,  H01L27/11206 ,  H01L29/66 ,  H01L29/7881

Abstract: A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

Abstract translation: 描述了由可编程衬底区域包围的具有金属氧化物半导体场效应晶体管（MOSFET）的可编程器件。 MOSFET具有由具有绝缘区域的沟道区域和设置在沟道区域上方的栅极分隔的源极和漏极区域。 设置在衬底区域内的接合部控制可编程衬底区域。 偏置连接点会耗尽衬底区域，从而将MOSFET的主体与次级阱隔离。 当结点保持不偏差时，MOSFET的主体电耦合到次级阱。

公开(公告)号：US08649209B1

公开(公告)日：2014-02-11

申请号：US13072530

申请日：2011-03-25

Applicant: Jun Liu ,  Qi Xiang

Inventor： Jun Liu ,  Qi Xiang

IPC: G11C11/00

CPC classification number: H01L29/78 ,  G11C11/412

Abstract: Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.

Abstract translation: 提供了具有存储器电路的集成电路。 存储器电路可以包括存储器单元晶体管和相关联的传输晶体管。 存储单元晶体管和传输晶体管可以使用并联耦合的多个氧化物定义（OD）区段形成。 多个OD条可以具有减小的宽度。 从相邻OD条到给定OD条的距离与给定OD条的宽度的比可以至少为0.5。 使用这种多条布置形成存储器电路晶体管可以提供提高晶体管性能的增加的应力水平。 每个OD条可以具有仍然满足制造设计规则的减小的宽度。 形成具有减小的宽度的OD区域允许传输晶体管在更高的电压电平下被过载驱动以进一步提高晶体管的性能。

公开(公告)号：US20120235662A1

公开(公告)日：2012-09-20

申请号：US13051648

申请日：2011-03-18

Applicant: Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

Inventor： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

IPC: G05F3/02

CPC classification number: G05F3/30

Abstract: A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.

Abstract translation: 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。

公开(公告)号：US08242581B1

公开(公告)日：2012-08-14

申请号：US12324793

申请日：2008-11-26

Applicant: Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

Inventor： Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

IPC: H01L29/93

CPC classification number: H01L29/94 ,  H01L29/4983 ,  H01L29/93

Abstract: Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.

Abstract translation: 提供混合栅极变容二极管。 混合栅极变容二极管可以包括给定掺杂型的半导体区域。 用于变容二极管的第一端可以由半导体区域上的栅极结构形成。 用于变容二极管的第二端子可以由具有与给定掺杂类型相同的掺杂类型的半导体区域中的重掺杂区域形成。 用于变容二极管的第三端子可以由具有与给定掺杂类型不同的掺杂类型的半导体区域中的重掺杂区域形成。 栅极结构可以包括栅极绝缘体上的多个栅极导体。 栅极绝缘体可以是高K电介质。 栅极导体可以是具有不同功函数的金属或其它材料。 诸如多晶硅层的导电层可电连接第一和第二栅极导体。

公开(公告)号：US07713834B2

公开(公告)日：2010-05-11

申请号：US12205361

申请日：2008-09-05

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07648886B2

公开(公告)日：2010-01-19

申请号：US10341863

申请日：2003-01-14

Applicant: Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫形成为能够减少锗除气的低温过程。 低温过程可以是UVO，ALD，CVD，PECVD或HDP工艺。

公开(公告)号：US07417250B1

公开(公告)日：2008-08-26

申请号：US11151550

申请日：2005-06-14

Applicant: James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

Inventor： James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L29/1054

Abstract: A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

Abstract translation: 制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。 应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，应变硅层的第一和第二部分最初可以具有相同的厚度。 在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。 还公开了一种半导体器件。

公开(公告)号：US07238588B2

公开(公告)日：2007-07-03

申请号：US10755746

申请日：2004-01-12

Applicant: Qi Xiang

Inventor： Qi Xiang

IPC: H01L21/762

CPC classification number: H01L21/02238 ,  C12N5/0623 ,  C12N2501/11 ,  C12N2501/115 ,  C12N2501/91 ,  C12N2501/999 ,  H01L21/02255 ,  H01L21/3081 ,  H01L21/31658 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is formed in a selective epitaxial growth (SEG) process. The SEG process can be a CVD or MBE process. Capping layers can be used above the strained silicon layer.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由在选择性外延生长（SEG）工艺中形成的半导体或金属层形成。 SEG过程可以是CVD或MBE过程。 可以在应变硅层之上使用封盖层。