公开(公告)号：US20210151394A1

公开(公告)日：2021-05-20

申请号：US17095277

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Yasutaka NAKASHIBA

IPC: H01L23/64 ,  H02J50/12 ,  H04B5/00 ,  H01L49/02 ,  H01L21/56

Abstract: The semiconductor device includes a first semiconductor substrate having a first surface and a second surface having a relationship with each other, a first circuit and electrically connected to the first circuit, and a first inductor formed at a position overlapping with the first semiconductor substrate, between the first surface and the first circuit, a first chip formed so as to cover the first surface, a second semiconductor substrate having a third surface and a fourth surface having a relationship with each other, a second circuit and electrically connected, and a second inductor formed so as to be electromagnetically coupled with the first inductor, the second surface, grooves are formed to reach the first insulating film, in a plan view, It is formed so as to surround the first circuit.

公开(公告)号：US20200243443A1

公开(公告)日：2020-07-30

申请号：US16743468

申请日：2020-01-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/498 ,  H01L27/22 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065

Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.

公开(公告)号：US20200043847A1

公开(公告)日：2020-02-06

申请号：US16505228

申请日：2019-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Teruhiro KUWAJIMA

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.

公开(公告)号：US20190196231A1

公开(公告)日：2019-06-27

申请号：US16182259

申请日：2018-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru KAWAI ,  Shinichi WATANUKI ,  Yasutaka NAKASHIBA

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F2201/063 ,  G02F2203/50

Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.

公开(公告)号：US20190196099A1

公开(公告)日：2019-06-27

申请号：US16183319

申请日：2018-11-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi WATANUKI ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  H01L23/532 ,  H01L21/02 ,  H01L25/16

CPC classification number: G02B6/1223 ,  H01L21/0214 ,  H01L21/02219 ,  H01L23/5329 ,  H01L25/167

Abstract: Two optical waveguides and an insulating film provided to cover the optical waveguides are formed over an insulating layer. Two wirings and a heater metal wire are formed over the insulating film via an insulating film different from the above insulating film. The latter insulating film is thinner than the former insulating film, and has a higher refractive index than the former insulating film. The leaked light from either of the two optical waveguides can be suppressed or prevented from being reflected by any one of the two wirings, the heater metal wire, and the like to travel again toward the two optical waveguides by utilizing the difference between the refractive indices of the two insulating films.

公开(公告)号：US20190165165A1

公开(公告)日：2019-05-30

申请号：US16263256

申请日：2019-01-31

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA ,  Yutaka AKIYAMA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L23/482 ,  H01L27/06 ,  H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L23/495 ,  H01L23/522

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

公开(公告)号：US20180308795A1

公开(公告)日：2018-10-25

申请号：US15953872

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA ,  Shinichi KUWABARA

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

公开(公告)号：US20180299706A1

公开(公告)日：2018-10-18

申请号：US15878619

申请日：2018-01-24

Applicant: Renesas Electronics Corporation

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA ,  Shinichi WATANUKI

IPC: G02F1/025 ,  H01L29/06 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/02

CPC classification number: G02F1/025 ,  G02F2001/0151 ,  G02F2201/302 ,  G02F2202/105 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/0657 ,  H01L29/16

Abstract: To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a MOS optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith. The projection of the grating coupler and the MOS optical modulator is formed of a first semiconductor layer, a second insulating layer, and a second semiconductor layer stacked successively on a first insulating layer, while the grating coupler and the MOS optical modulator each have a slab portion formed of the first semiconductor layer.

公开(公告)号：US20180136390A1

公开(公告)日：2018-05-17

申请号：US15785560

申请日：2017-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  H01L33/62 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/12002 ,  G02B6/4274 ,  G02B2006/12126 ,  G02B2006/12197 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0033 ,  H01L2933/0066

Abstract: In a semiconductor device, first dummy patterns including a different material from transmission lines (first optical waveguide and second optical waveguide) are formed in a first region close to the transmission lines, and second dummy patterns, which include the same material as the transmission lines and do not function as the transmission lines, are formed in a second region apart from the transmission lines.

公开(公告)号：US20170256602A1

公开(公告)日：2017-09-07

申请号：US15598475

申请日：2017-05-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA

IPC: H01L49/02 ,  G01R31/28 ,  G01R31/303 ,  G01R31/302 ,  H02J17/00

CPC classification number: H01L28/10 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor chip formation region, a chip internal circuit provided within the semiconductor chip formation region of the semiconductor substrate, a signal transmitting/receiving unit which is provided within the semiconductor chip formation region of the semiconductor substrate, transmits/receives a signal to/from an outside in a non-contact manner by one of electromagnetic induction and capacitive coupling, and transmits/receives a signal to/from the chip internal circuit through electrical connection to the chip internal circuit, and a power receiving inductor which has a diameter provided along an outer edge of the semiconductor chip formation region of the semiconductor substrate so as to surround the chip internal circuit and the signal transmitting/receiving unit, receives a power supply signal from the outside in the non-contact manner, and is electrically connected to the chip internal circuit.