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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190006535A1

    公开(公告)日：2019-01-03

    申请号：US15980661

    申请日：2018-05-15

    Applicant: Renesas Electronics Corporation

    Inventor： Teruhiro KUWAJIMA ,  Shinichi WATANUKI ,  Futoshi KOMATSU ,  Tomoo NAKAYAMA

    IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/024 ,  H01L31/02 ,  H01L31/028 ,  G02B6/43 ,  G02F1/025

    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film. A wire formed over a second interlayer insulating film is electrically coupled with the heater and the first and second contact portions via plugs embedded in the second interlayer insulating film.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190198703A1

    公开(公告)日：2019-06-27

    申请号：US16188985

    申请日：2018-11-13

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Tomoo NAKAYAMA ,  Shinichi WATANUKI ,  Futoshi KOMATSU ,  Teruhiro KUWAJIMA ,  Takashi OGURA ,  Hiroyuki OKUAKI ,  Shigeaki SHIMIZU

    IPC: H01L31/105 ,  H01L31/18 ,  G02B6/122 ,  G02B6/136

    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190206789A1

    公开(公告)日：2019-07-04

    申请号：US16192521

    申请日：2018-11-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Teruhiro KUWAJIMA ,  Yasutaka NAKASHIBA ,  Akira MATSUMOTO ,  Akio ONO ,  Tetsuya IIDA

    IPC: H01L23/522 ,  H01L49/02 ,  H01L29/93 ,  H01L27/06 ,  H03L7/099

    CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/93 ,  H03L7/099

    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the cod is 7 μm or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 μm or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view. Even if such wirings (linear wiring parts) are arranged under the coil, the characteristics (for example, RF characteristics) of the semiconductor device are not deteriorated. In addition, the area of the semiconductor device can be reduced or high integration of elements can be realized by laminating elements (for example, MOM capacitance elements and the like) having the coil and the linear wiring parts.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180294222A1

    公开(公告)日：2018-10-11

    申请号：US16009429

    申请日：2018-06-15

    Applicant: Renesas Electronics Corporation

    Inventor： Teruhiro KUWAJIMA ,  Akira MATSUMOTO ,  Yasutaka NAKASHIBA ,  Takashi IWADARE

    IPC: H01L23/522

    CPC classification number: H01L23/5227 ,  H01L23/4952 ,  H01L23/49551 ,  H01L2224/05554 ,  H01L2224/4813 ,  H01L2224/49175

    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20170062332A1

    公开(公告)日：2017-03-02

    申请号：US15186734

    申请日：2016-06-20

    Applicant: Renesas Electronics Corporation

    Inventor： Teruhiro KUWAJIMA ,  Akira MATSUMOTO ,  Yasutaka NAKASHIBA ,  Takashi IWADARE

    IPC: H01L23/522

    CPC classification number: H01L23/5227 ,  H01L23/4952 ,  H01L23/49551 ,  H01L2224/05554 ,  H01L2224/4813 ,  H01L2224/49175

    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

    Abstract translation: SOP具有半导体芯片。 芯片包括一对下层线圈和层叠在其间形成的层间绝缘膜的上层线圈，电耦合到上层线圈的第一电路单元和多个电极焊盘。 此外，它具有用于电耦合上层线圈和第一电路单元的导线，布置在半导体芯片周围的多个内部引线和外部引线，用于电连接半导体芯片的电极焊盘和内部 引线和用于覆盖半导体芯片的树脂制密封构件。 电线沿电线的延伸方向延伸。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150108655A1

    公开(公告)日：2015-04-23

    申请号：US14508776

    申请日：2014-10-07

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Teruhiro KUWAJIMA

    IPC: H01L23/498 ,  H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring.

    Abstract translation: 同时实现布线槽的嵌入性的提高和布线与耦合构件之间的耦合故障的产生的抑制。 在垂直于穿过接触件的方向和第二布线延伸的方向的横截面中，接触的中心比第二布线的中心更靠近第二布线的第一侧表面。 此外，当第二配线的第一侧表面与第二布线延伸的方向上的接触重叠的区域被设置为重叠区域时，至少重叠区域的下部的倾斜比 第二布线的侧表面的其它部分。

    SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230275051A1

    公开(公告)日：2023-08-31

    申请号：US17993350

    申请日：2022-11-23

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Teruhiro KUWAJIMA

    IPC: H01L23/00

    CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05573 ,  H01L2224/02141 ,  H01L2224/02126 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644

    Abstract: A semiconductor device capable of suppressing formation of nodules on an upper surface of an electroless plating film will be provided. The semiconductor device includes a wiring, a cap film, a passivation film, a shielding film, and the electroless plating film. The wiring has a bonding pad. The passivation film is disposed so as to cover the wiring and the cap film. An opening penetrates through the passivation film and the cap film, and partially expose an upper surface of the bonding pad. The upper surface of the bonding pad exposed from the opening is divided into a first region and a second region. The shielding film is disposed on the second region. The electroless plating film is disposed on the first region and the shielding film.

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