公开(公告)号：US07241647B2

公开(公告)日：2007-07-10

申请号：US10919952

申请日：2004-08-17

申请人： Mariam G. Sadaka ,  Shawn G. Thomas ,  Ted R. White ,  Chun-Li Liu ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean

发明人： Mariam G. Sadaka ,  Shawn G. Thomas ,  Ted R. White ,  Chun-Li Liu ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean

IPC分类号： H01L21/00

CPC分类号： H01L29/78687 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66742

摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

摘要翻译： 一种形成半导体器件的方法。 该方法包括形成用于形成应变硅层的模板层。 在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。 当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。 由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

公开(公告)号：US07208357B2

公开(公告)日：2007-04-24

申请号：US10919922

申请日：2004-08-17

申请人： Mariam G. Sadaka ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

发明人： Mariam G. Sadaka ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/425

CPC分类号： H01L29/161 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/1054 ,  Y10S438/933

摘要： A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.

摘要翻译： 一种形成应变半导体层的工艺。 该方法包括在层之前进行冷凝过程之前将离子注入到半导体层中。 离子有助于半导体层中的原子（例如锗）的扩散并增加半导体层的松弛。 在冷凝过程之后，该层可用作形成应变半导体层的模板层。

公开(公告)号：US07141857B2

公开(公告)日：2006-11-28

申请号：US10883180

申请日：2004-06-30

申请人： Zhiyi Yu ,  Jay A. Curless ,  Yong Liang ,  Alexandra Navrotsky ,  Sergey Ushakov ,  Bich-Yen Nguyen ,  Alexander Demkov

发明人： Zhiyi Yu ,  Jay A. Curless ,  Yong Liang ,  Alexandra Navrotsky ,  Sergey Ushakov ,  Bich-Yen Nguyen ,  Alexander Demkov

IPC分类号： H01L29/94 ,  H01L21/469

CPC分类号： H01L21/02181 ,  C23C14/0026 ,  C23C14/083 ,  H01L21/02192 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/3115 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517

摘要： Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series metal-containing dopant is comprised within the amorphous layer of hafnium oxide. The process comprises growing an amorphous layer of hafnium oxide overlying a substrate. The amorphous layer of hafnium oxide is doped with a dopant having the chemical formulation LnOx, where Ln is lanthanum, a lanthanide-series metal, or a combination thereof, and X is any number greater than zero. The doping step may be performed during or after growth of the amorphous layer of hafnium oxide.

公开(公告)号：US20060228872A1

公开(公告)日：2006-10-12

申请号：US11093645

申请日：2005-03-30

申请人： Bich-Yen Nguyen ,  Shawn Thomas ,  Lubomir Cergel ,  Mariam Sadaka ,  Voon-Yew Thean ,  Peter Wennekers ,  Ted White ,  Andreas Wild ,  Detlev Gruetzmacher ,  Oliver Schmidt

发明人： Bich-Yen Nguyen ,  Shawn Thomas ,  Lubomir Cergel ,  Mariam Sadaka ,  Voon-Yew Thean ,  Peter Wennekers ,  Ted White ,  Andreas Wild ,  Detlev Gruetzmacher ,  Oliver Schmidt

IPC分类号： H01L21/20

CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687

摘要： A method of forming a semiconductor device includes forming a local strain-inducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is formed over the dielectric layer and the local strain inducing structure, wherein formation of a first portion of the second material over the dielectric layer provides a poly crystalline structure of the second material and wherein formation of a second portion of the second material over the local strain-inducing structure provides a single crystalline structure of the second material subject to mechanical strain by the surface of the local strain-inducing structure. The single crystalline structure serves as a strained semiconductor layer of the semiconductor device.

摘要翻译： 形成半导体器件的方法包括在电介质层内的点位置形成第一半导体材料的局部应变诱导结构。 局部应变诱导结构具有规定的几何形状，其表面设置在电介质层的表面之上。 第二半导体材料形成在电介质层和局部应变诱导结构之上，其中第二材料的第一部分在电介质层上的形成提供了第二材料的多晶结构，并且其中形成第二材料的第二部分 局部应变诱导结构上的材料提供由局部应变诱导结构的表面经受机械应变的第二材料的单晶结构。 单晶结构用作半导体器件的应变半导体层。

公开(公告)号：US20060226492A1

公开(公告)日：2006-10-12

申请号：US11094008

申请日：2005-03-30

申请人： Bich-Yen Nguyen ,  Shawn Thomas ,  Lubomir Cergel ,  Mariam Sadaka ,  Voon-Yew Thean ,  Peter Wennekers ,  Ted White ,  Andreas Wild ,  Detlev Gruetzmacher ,  Oliver Schmidt

发明人： Bich-Yen Nguyen ,  Shawn Thomas ,  Lubomir Cergel ,  Mariam Sadaka ,  Voon-Yew Thean ,  Peter Wennekers ,  Ted White ,  Andreas Wild ,  Detlev Gruetzmacher ,  Oliver Schmidt

IPC分类号： H01L29/94

CPC分类号： H01L29/78696 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687

摘要： A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. In addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.

摘要翻译： 半导体器件包括机械应变通道，其中通道包括具有非线性几何形状的应变半导体层的单晶结构，非线性几何形状包括拱形部分。 所述半导体器件还包括介电层，其中所述沟道的第一部分设置在所述电介质层内的点位置上方，并且所述沟道的第二部分设置在所述电介质层的靠近所述点位置和外部的位置 。 此外，栅极靠近通道设置，用于控制电流通过耦合到通道的第一和第二电流处理电极之间的通道。

公开(公告)号：US06518106B2

公开(公告)日：2003-02-11

申请号：US09865855

申请日：2001-05-26

申请人： Tat Ngai ,  Bich-Yen Nguyen ,  Vidya S. Kaushik ,  Jamie K. Schaeffer

发明人： Tat Ngai ,  Bich-Yen Nguyen ,  Vidya S. Kaushik ,  Jamie K. Schaeffer

IPC分类号： H01L2100

CPC分类号： H01L21/823842

摘要： A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.

公开(公告)号：US06509609B1

公开(公告)日：2003-01-21

申请号：US09884345

申请日：2001-06-18

申请人： Yaohui Zhang ,  Bich-Yen Nguyen ,  Kuntal Joardar ,  Daniel Thanh-Khac Pham

发明人： Yaohui Zhang ,  Bich-Yen Nguyen ,  Kuntal Joardar ,  Daniel Thanh-Khac Pham

IPC分类号： H01L2978

CPC分类号： H01L29/66643 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7839

摘要： A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/&mgr;m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL

摘要翻译： 沟槽沟道肖特基接触MOSFET具有不对称的源极和漏极区域。 MOSFET包括背景掺杂浓度小于约1017cm-3的未掺杂硅衬底。 在基板的第一表面中形成开槽通道。 第一金属硅化物材料形成在带槽沟道的第一侧，形成源极区，并且第二金属硅化物材料形成在带槽沟道的第二侧上，形成漏区。 在沟槽通道中形成金属门。 带槽结构允许关断状态电流降低到小于50pA / mum。 此外，特征尺寸可以缩小到10nm，而没有强的短信道效应（DIBL <0.063），并且门延迟（CV / I）降低到2.4ps。

公开(公告)号：US6084279A

公开(公告)日：2000-07-04

申请号：US831287

申请日：1997-03-31

申请人： Bich-Yen Nguyen ,  J. Olufemi Olowolafe ,  Bikas Maiti ,  Olubunmi Adetutu ,  Philip J. Tobin

发明人： Bich-Yen Nguyen ,  J. Olufemi Olowolafe ,  Bikas Maiti ,  Olubunmi Adetutu ,  Philip J. Tobin

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244 ,  H01L23/31 ,  H01L29/49 ,  H01L21/338

CPC分类号： H01L27/11 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/28568 ,  H01L21/76895 ,  H01L21/82345 ,  H01L23/3171 ,  H01L29/4925 ,  H01L29/4966 ,  H01L2924/0002

摘要： Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

摘要翻译： 金属半导体氮化物栅电极（40,70）形成用于半导体器件（60）。 栅电极（40,70）可以通过溅射沉积，低压化学气相沉积（LPCVD）或等离子体增强化学气相沉积（PECVD）来形成。 预期这些材料将类似于含硅化合物蚀刻，并且可以在传统的基于卤化物的蚀刻化学中进行蚀刻。 金属半导体氮化物栅电极（40,70）相对稳定，可以形成为比传统栅极电极（40,70）更靠近工作功能，并且靠近用于衬底（12）的材料的带隙中间的功函数。

公开(公告)号：US5567958A

公开(公告)日：1996-10-22

申请号：US452944

申请日：1995-05-31

申请人： Marius Orlowski ,  James D. Hayden ,  Bich-Yen Nguyen

发明人： Marius Orlowski ,  James D. Hayden ,  Bich-Yen Nguyen

IPC分类号： H01L21/336 ,  H01L27/11 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L27/1108 ,  H01L29/66757 ,  H01L29/78696 ,  Y10S257/903

摘要： A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.

摘要翻译： 薄膜晶体管和SRAM存储单元包括由开口（22）和上覆绝缘层（11）分开的薄膜源区和漏区（12,14）。 薄膜通道层（16）覆盖薄膜源区和漏区（12,14），绝缘层（11）的一部分由开口（22）露出。 薄膜栅电极（20）位于开口（22）中并且在薄膜通道层（16）中限定薄膜通道区（24）。 薄膜栅电极（20）通过栅介质层（18）与薄膜沟道区（24）分离。 薄膜通道区域（24）沿薄膜源极和漏极区域（12,14）的垂直壁表面（26,28）延伸，为薄膜晶体管提供延长的沟道长度。

公开(公告)号：US5543635A

公开(公告)日：1996-08-06

申请号：US455268

申请日：1995-05-31

申请人： Bich-Yen Nguyen ,  Thomas F. McNelly ,  Philip J. Tobin ,  James D. Hayden

发明人： Bich-Yen Nguyen ,  Thomas F. McNelly ,  Philip J. Tobin ,  James D. Hayden

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L29/76 ,  H01L29/04 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/66765 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78678 ,  Y10S148/109

摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

摘要翻译： 使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。 在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。 然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区 （52）内。