公开(公告)号：US20130140669A1

公开(公告)日：2013-06-06

申请号：US13691800

申请日：2012-12-02

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

Abstract translation: 在SOI衬底上形成作为半导体元件的第一MISFET。 SOI衬底包括作为基底的支撑衬底，BOX层，其是形成在支撑衬底的主表面（表面）上的绝缘层，即掩埋氧化物膜; 以及作为在BOX层上形成的半导体层的SOI层。 作为半导体元件的第一MISFET形成于SOI层。 在隔离区域中，穿过SOI层和BOX层形成隔离槽，使得槽的底面位于支撑基板的厚度的中间。 隔离膜被埋在正在形成的隔离槽中。 然后，在BOX层和隔离膜之间插入抗氧化膜。

公开(公告)号：US20130119470A1

公开(公告)日：2013-05-16

申请号：US13678103

申请日：2012-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuyuki HORITA ,  Toshiaki IWAMATSU ,  Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L29/78 ,  H01L21/48

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/486 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

公开(公告)号：US20210257459A1

公开(公告)日：2021-08-19

申请号：US17224743

申请日：2021-04-07

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.
A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20200066757A1

公开(公告)日：2020-02-27

申请号：US16670918

申请日：2019-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20180350844A1

公开(公告)日：2018-12-06

申请号：US16040305

申请日：2018-07-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42356 ,  H01L29/66545

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

公开(公告)号：US20180019260A1

公开(公告)日：2018-01-18

申请号：US15695410

申请日：2017-09-05

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20170365330A1

公开(公告)日：2017-12-21

申请号：US15620406

申请日：2017-06-12

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: G11C11/417 ,  H01L27/12 ,  H01L27/11

CPC classification number: G11C11/417 ,  G05F3/205 ,  G11C5/146 ,  H01L21/823892 ,  H01L27/0222 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

Abstract: A semiconductor device includes a substrate, a circuit having a transistor formed on the substrate, an oscillation circuit generating a frequency signal, a substrate voltage generation circuit generating a substrate voltage in accordance with the frequency signal from the oscillation circuit, and a control circuit varying a frequency of the frequency signal from the oscillation circuit during a stand-by period of the circuit.

公开(公告)号：US20150340082A1

公开(公告)日：2015-11-26

申请号：US14715636

申请日：2015-05-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/413 ,  G11C2207/2227 ,  H01L21/84 ,  H01L27/1108 ,  H01L27/1203

Abstract: An intermediate mode is set between the active mode in which a threshold voltage is low and a standby mode in which a threshold voltage is high. When a mode is shifted from the active mode to the standby mode, the threshold voltage for the active mode is raised temporarily to a threshold voltage for the intermediate mode and then the threshold voltage for the intermediate mode is raised to the threshold voltage for the standby mode. When a mode is shifted from the standby mode to the active mode, the threshold voltage for the standby mode is lowered temporarily to the threshold voltage for the intermediate mode and then the threshold voltage for the intermediate mode is lowered to the threshold voltage for the active mode.

Abstract translation: 在阈值电压低的活动模式和阈值电压高的待机模式之间设定中间模式。 当模式从活动模式切换到待机模式时，主动模式的阈值电压暂时升高到中间模式的阈值电压，然后中间模式的阈值电压升高到待机模式的阈值电压 模式。 当模式从待机模式转换到活动模式时，待机模式的阈值电压临时降低到中间模式的阈值电压，然后中间模式的阈值电压降低到活动的阈值电压 模式。

公开(公告)号：US20150221560A1

公开(公告)日：2015-08-06

申请号：US14686828

申请日：2015-04-15

Applicant: Renesas Electronics Corporation

Inventor： Katsuyuki HORITA ,  Toshiaki IWAMATSU ,  Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L21/84 ,  H01L21/768 ,  H01L21/28 ,  H01L21/283 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/486 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

Abstract translation: 提高了半导体器件的特性。 本发明的半导体器件包括：（a）布置在由元件隔离区包围的半导体区域形成的有源区中的MISFET; 和（b）布置在有源区下方的绝缘层。 此外，半导体器件包括：（c）布置在有源区下方以插入绝缘层的p型半导体区域; 和（d）布置在p型半导体区域下方的导电类型与p型相反的n型半导体区域。 并且，p型半导体区域包括从绝缘层的下方延伸的连接区域，并且MIS型的p型半导体区域和栅极电极通过作为一体形成的导电膜的共享插头彼此连接 从栅电极上方延伸到连接区域的上方。

公开(公告)号：US20130187230A1

公开(公告)日：2013-07-25

申请号：US13747537

申请日：2013-01-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。