公开(公告)号：US20190206867A1

公开(公告)日：2019-07-04

申请号：US16030224

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Han LEE ,  Sungchul Park ,  Yunil Lee ,  Byoung-gi Kim ,  Yeongmin Jeon ,  Daewon Ha ,  Inchan Hwang ,  Jae Hyun Park ,  Woocheol Shin

IPC: H01L27/092 ,  H01L29/423 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor substrate includes a plurality of gate electrodes crossing active patterns on a substrate and extending in a second direction, the gate electrodes spaced apart in the second direction from each other, a gate separation pattern having a major axis in the first direction and between two of the gate electrodes, the two of the gate electrodes adjacent to each other in the second direction, and a plurality of gate spacers covering sidewalls of respective ones of the gate electrodes, the gate spacers crossing the gate separation pattern and extending in the second direction. The gate separation pattern includes a lower portion extending in the first direction, an intermediate portion protruding from the lower portion and having a first width, and an upper portion between two adjacent gate spacers and protruding from the intermediate portion, the upper portion having a second width less than the first width.

公开(公告)号：US12200920B2

公开(公告)日：2025-01-14

申请号：US17816809

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan Hwang ,  Jaemyung Choi ,  Kang-Ill Seo

IPC: G11C16/04 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.

公开(公告)号：US12144163B2

公开(公告)日：2024-11-12

申请号：US17382060

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US11968818B2

公开(公告)日：2024-04-23

申请号：US17345504

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan Hwang ,  Hwichan Jun

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L23/5286 ,  H01L27/0922 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/78696

Abstract: A semiconductor device including a static random access memory (SRAM) in a three-dimensional (3D) stack is provided. The semiconductor device includes a first transistor stack including a first channel and a first gate, a second transistor stack including a second channel and a second gate, the second transistor stack being disposed above the first transistor stack, a bit line disposed on a first portion of an upper surface of the first channel, a voltage source disposed on a first portion of an upper surface of the second channel and a first shared contact connecting the first channel to the second channel, where a width of the second channel is less than a width of the first channel.

公开(公告)号：US20230343823A1

公开(公告)日：2023-10-26

申请号：US17882203

申请日：2022-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaejik BAEK ,  Byounghak Hong ,  Inchan Hwang ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/78696

Abstract: Provided is a multi-stack semiconductor device including: a substrate; a lower nanosheet transistor including a lower channel structure; a lower gate structure surrounding the lower channel structure and including a gate dielectric layer; lower source/drain regions at both ends of the lower channel structure; and at least one lower inner spacer isolating the lower source/drain regions from the lower gate structure; an upper nanosheet transistor, on the lower nanosheet transistor, including an upper channel structure; an upper gate structure surrounding the upper channel structure and including the gate dielectric layer; upper source/drain regions at both ends of the upper channel structure; and at least one upper inner spacer isolating the upper source/drain regions from the upper gate structure; and an isolation structure between the lower and upper channel structures, wherein a spacer structure including a same material forming the lower or upper inner spacer is formed at a side of the isolation structure.

公开(公告)号：US20230275021A1

公开(公告)日：2023-08-31

申请号：US17738393

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Jeonghyuk Yim ,  Inchan Hwang ,  Gilhwan Son ,  Seungyoung Lee ,  Saehan Park ,  Janggeun Lee ,  Myunghoon Jung ,  Seungchan Yun ,  Buhyun Ham ,  Kang-ILL Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/302 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L23/5226 ,  H01L21/302 ,  H01L21/823475

Abstract: Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

公开(公告)号：US11670677B2

公开(公告)日：2023-06-06

申请号：US17148252

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwichan Jun ,  Inchan Hwang ,  Byounghak Hong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

公开(公告)号：US20230135219A1

公开(公告)日：2023-05-04

申请号：US17570920

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd

Inventor： Byounghak Hong ,  Seungchan Yun ,  Inchan Hwang ,  Hyoeun Park ,  Kang-ill Seo

IPC: H01L27/07 ,  H01L27/08 ,  H01L27/06 ,  H01L49/02 ,  H01L25/07

Abstract: Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

公开(公告)号：US20230095421A1

公开(公告)日：2023-03-30

申请号：US17547700

申请日：2021-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Hoonseok Seo ,  Seungchan Yun ,  Inchan Hwang ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/48 ,  H01L21/8234 ,  H01L49/02

Abstract: Integrated circuit devices including a metal resistor and methods of forming the same are provided. The integrated circuit devices may include a substrate including a first surface and a second surface that is opposite the first surface and is parallel to the first surface, a transistor including a gate electrode, first and second resistor contacts that are spaced apart from each other in a horizontal direction that is parallel to the second surface of the substrate, and a metal resistor. The first surface of the substrate may face the gate electrode. The metal resistor may include a third surface and a fourth surface that is parallel to the third surface and the second surface of the substrate, and the fourth surface of the metal resistor may be closer to the second surface than the first surface and contacts the first and second resistor contacts.

公开(公告)号：US11437369B2

公开(公告)日：2022-09-06

申请号：US17147587

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan Hwang ,  Hwichan Jun

IPC: H01L27/085 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/822

Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.