公开(公告)号：US10535412B2

公开(公告)日：2020-01-14

申请号：US15963647

申请日：2018-04-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Jianzhi Wu ,  Gerrit Jan Hemink

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/10

Abstract: A memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.

公开(公告)号：US11894037B2

公开(公告)日：2024-02-06

申请号：US17718759

申请日：2022-04-12

Applicant: SanDisk Technologies LLC

Inventor： Michael Grobis ,  James W. Reiner ,  Michael Nicolas Albert Tran ,  Juan P. Saenz ,  Gerrit Jan Hemink

IPC: G11C13/00 ,  G11C11/16 ,  G11C7/20 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: G11C11/1659 ,  G11C7/20 ,  G11C13/003 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.

公开(公告)号：US11342028B2

公开(公告)日：2022-05-24

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US11101326B2

公开(公告)日：2021-08-24

申请号：US16896946

申请日：2020-06-09

Applicant: SanDisk Technologies LLC

Inventor： Federico Nardi ,  Christopher J Petti ,  Gerrit Jan Hemink

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  G11C11/56 ,  H01L29/786

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

公开(公告)号：US20210050054A1

公开(公告)日：2021-02-18

申请号：US16540862

申请日：2019-08-14

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Peter Rabkin ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C11/56 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408

Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

公开(公告)号：US20200234768A1

公开(公告)日：2020-07-23

申请号：US16283464

申请日：2019-02-22

Applicant: SanDisk Technologies LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Tai-Yuan Tseng ,  Henry Chin ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

公开(公告)号：US20200034697A1

公开(公告)日：2020-01-30

申请号：US16368347

申请日：2019-03-28

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi ,  Pi-Feng Chiu ,  Wen Ma ,  Minghai Qin ,  Gerrit Jan Hemink ,  Martin Lueker-Boden

IPC: G06N3/063 ,  G11C16/04 ,  G11C16/26

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

公开(公告)号：US10262730B1

公开(公告)日：2019-04-16

申请号：US15869553

申请日：2018-01-12

Applicant: SanDisk Technologies LLC

Inventor： Federico Nardi ,  Christopher J Petti ,  Gerrit Jan Hemink

IPC: G11C11/00 ,  G11C13/00

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

公开(公告)号：US20170372789A1

公开(公告)日：2017-12-28

申请号：US15194295

申请日：2016-06-27

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.

公开(公告)号：US09805809B1

公开(公告)日：2017-10-31

申请号：US15253864

申请日：2016-08-31

Applicant: SanDisk Technologies LLC

Inventor： Zhenming Zhou ,  Guirong Liang ,  Gerrit Jan Hemink ,  Dana Lee ,  Chandu Gorla ,  Sarath Puthenthermadam ,  Deepanshu Dutta

IPC: G11C16/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3427

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells comprising a plurality of word lines. A controller is configured to perform a read operation on one or more word lines adjacent to a target word line. A controller is configured to determine a read setting for application to a target word line based on a result of a read operation on one or more word lines adjacent to the target word line. A controller is configured to perform a read operation on a target word line using a determined read setting.