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    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME
    32.
    发明申请
    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME 有权

    公开(公告)号：US20230129594A1

    公开(公告)日：2023-04-27

    申请号：US17566262

    申请日：2021-12-30

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fumitaka AMANO

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

    Abstract: A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.

    THREE-DIMENSIONAL MEMORY ARRAY INCLUDING DUAL WORK FUNCTION FLOATING GATES AND METHOD OF MAKING THE SAME
    34.
    发明申请
    THREE-DIMENSIONAL MEMORY ARRAY INCLUDING DUAL WORK FUNCTION FLOATING GATES AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20220254798A1

    公开(公告)日：2022-08-11

    申请号：US17351720

    申请日：2021-06-18

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Ramy Nashed Bassely SAID ,  Yanli ZHANG ,  Jiahui YUAN ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA

    IPC: H01L27/11556 ,  H01L29/49

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF FORMING THE SAME
    37.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210327897A1

    公开(公告)日：2021-10-21

    申请号：US17090420

    申请日：2020-11-05

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yuki KASAI ,  Shigehisa INOUE ,  Tomohiro ASANO ,  Raghuveer S. MAKALA

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

    Abstract: An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to the silicon nitride layers and the memory opening fill structures. Insulating layers comprising silicon oxide are formed by oxidizing surface portions of the silicon nitride layers and portions of the charge storage material layers that are proximal to the laterally-extending cavities. Remaining portions of the charge storage material layers form vertical stacks of discrete charge storage elements. Remaining portions of the silicon nitride layers are replaced with electrically conductive layers.

    SEMICONDUCTOR STRUCTURE CONTAINING REENTRANT SHAPED BONDING PADS AND METHODS OF FORMING THE SAME
    38.
    发明申请
    SEMICONDUCTOR STRUCTURE CONTAINING REENTRANT SHAPED BONDING PADS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210296284A1

    公开(公告)日：2021-09-23

    申请号：US16825304

    申请日：2020-03-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Fei ZHOU

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

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