公开(公告)号：US20200243329A1

公开(公告)日：2020-07-30

申请号：US16505925

申请日：2019-07-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Michael J. SEDDON

IPC: H01L21/027 ,  H01L21/3213 ,  H01L21/78 ,  H01L21/311

Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.

公开(公告)号：US20190267344A1

公开(公告)日：2019-08-29

申请号：US15903677

申请日：2018-02-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuo OKADA ,  Hideaki YOSHIMI ,  Naoyuki YOMODA ,  Yusheng LIN

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/78

Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.

公开(公告)号：US20190067164A1

公开(公告)日：2019-02-28

申请号：US15813710

申请日：2017-11-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Hideyuki INOTSUME ,  Kazuo OKADA

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/304 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/288 ,  H01L21/683 ,  H01L21/78

Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.

公开(公告)号：US20180151526A1

公开(公告)日：2018-05-31

申请号：US15871586

申请日：2018-01-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00 ,  H01L21/48 ,  B23K3/06

CPC classification number: H01L24/11 ,  B23K3/0623 ,  H01L21/4853 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/03 ,  H01L2224/11

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.