公开(公告)号：US20180076332A1

公开(公告)日：2018-03-15

申请号：US15814925

申请日：2017-11-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Motomu KURATA ,  Yuta ENDO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/8258 ,  H01L22/12 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.

公开(公告)号：US20180013004A1

公开(公告)日：2018-01-11

申请号：US15696231

申请日：2017-09-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Takashi HAMADA ,  Akihisa SHIMOMURA ,  Satoru OKAMOTO ,  Katsuaki TOCHIBAYASHI

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  H01L21/4763 ,  H01L21/4757 ,  H01L29/66 ,  H01L21/465

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

公开(公告)号：US20170125455A1

公开(公告)日：2017-05-04

申请号：US15298307

申请日：2016-10-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L27/146 ,  H01L29/786 ,  H01L27/105

CPC classification number: H01L27/1288 ,  H01L27/1052 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/14616 ,  H01L29/7869

Abstract: Provided is a semiconductor device which can reduce leakage of current between wirings. Included steps are forming a first insulator over a first conductor which is formed over substrate; forming a first hard mask thereover; forming a first resist mask comprising a first opening, over the first hard mask; etching the first hard mask to form a second hard mask comprising a second opening; etching the first insulator using the second hard mask to form a second insulator comprising a third opening; forming a second conductor embedded in the second opening and the third opening; performing polishing treatment on the second hard mask and the second conductor to form a third conductor embedded in the third opening; forming a fourth conductor thereover; forming a second resist mask in a pattern over the fourth conductor; and dry-etching the fourth conductor to form a fifth conductor. The second hard mask can be dry-etched.

公开(公告)号：US20160307777A1

公开(公告)日：2016-10-20

申请号：US15092973

申请日：2016-04-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Ryota HODO ,  Yuta IIDA ,  Satoru OKAMOTO

IPC: H01L21/4757 ,  H01L21/473 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/76814 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L2221/1063

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Abstract translation: 提供一分钟晶体管。 提供具有低寄生电容的晶体管。 提供具有高频特性的晶体管。 提供包括晶体管的电极。 提供了一种新颖的电极。 电极包括含有金属的第一导电层，绝缘层和第二导电层。 绝缘层形成在第一导电层上。 在绝缘层上形成掩模层。 使用掩模层作为掩模的等离子体蚀刻绝缘层，由此在绝缘层中形成开口以到达第一导电层。 在氧气氛中至少对开口进行等离子体处理。 通过等离子体处理，在开口中的第一导电层上形成含金属的氧化物。 除去氧化物，然后在开口中形成第二导电层。

公开(公告)号：US20160233340A1

公开(公告)日：2016-08-11

申请号：US15017831

申请日：2016-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihisa SHIMOMURA ,  Satoru OKAMOTO ,  Yutaka OKAZAKI ,  Yoshinobu ASAMI ,  Hiroaki HONDA ,  Takuya TSURUME

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L21/385 ,  H01L27/1225 ,  H01L29/0688 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.

Abstract translation: 提供具有良好电特性的晶体管。 提供具有稳定电特性的晶体管。 提供了具有高集成度的半导体器件。 其中沟道形成的氧化物半导体层的侧表面被氧化物半导体层覆盖，从而可以防止从氧化物半导体的侧表面向内部的杂质扩散。 栅电极通过镶嵌工艺形成，由此可以以高密度小型化和形成晶体管。

公开(公告)号：US20220262438A1

公开(公告)日：2022-08-18

申请号：US17629801

申请日：2020-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hideki UOCHI ,  Satoru OKAMOTO

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/786

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US20220020883A1

公开(公告)日：2022-01-20

申请号：US17428825

申请日：2020-02-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuichi YANAGISAWA ,  Ryota HODO ,  Satoru OKAMOTO

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second insulator provided between the first insulator and the first oxide, a second oxide in contact with the first insulator and in contact with a side surface of the first oxide, and a third insulator over the first insulator, the second oxide, and the first oxide. The third insulator includes a region in contact with a top surface of the first oxide. The second insulator and the third insulator include a material which is less likely to pass oxygen than the second oxide.

公开(公告)号：US20210366926A1

公开(公告)日：2021-11-25

申请号：US17319389

申请日：2021-05-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US20190393079A1

公开(公告)日：2019-12-26

申请号：US16556330

申请日：2019-08-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Ryota HODO ,  Yuta IIDA ,  Satoru OKAMOTO

IPC: H01L21/768

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

公开(公告)号：US20190115478A1

公开(公告)日：2019-04-18

申请号：US16214197

申请日：2018-12-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/78693 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.