公开(公告)号：US20190287587A1

公开(公告)日：2019-09-19

申请号：US16194834

申请日：2018-11-19

Applicant: SK hynix Inc.

Inventor： Dong Hyun KIM ,  Dae Han KWON ,  Kwan Su SHON ,  Soon Ku KANG ,  Jung Hyun SHIN ,  Doo Bock LEE ,  Yo Han JEONG ,  Eun Ji CHOI ,  Tae Jin HWANG

IPC: G11C7/22 ,  G11C7/10

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

公开(公告)号：US20180115340A1

公开(公告)日：2018-04-26

申请号：US15443665

申请日：2017-02-27

Applicant: SK hynix Inc.

Inventor： Dae Han KWON

IPC: H04B1/401 ,  H04B7/08 ,  H04B17/364 ,  H03K3/356 ,  H04L25/03

CPC classification number: H04B1/401 ,  H03F3/245 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/405 ,  H03K3/356034 ,  H03K2005/00013 ,  H03K2005/00156 ,  H04B7/0828 ,  H04B17/364 ,  H04L25/03343

Abstract: A receiving device may include a buffer, a summer circuit, a first delay cell, and a second delay cell. The buffer may receive an external signal. The summer circuit may sum an output of the buffer, a first feedback signal, and a second feedback signal. The first delay cell may generate the first feedback signal by delaying an output of the summer circuit. The second delay cell may generate the second feedback signal by delaying the first feedback signal. The delay amounts of the first and second delay cells may be set based on a delay control voltage.

公开(公告)号：US20170272064A1

公开(公告)日：2017-09-21

申请号：US15233025

申请日：2016-08-10

Applicant: SK hynix Inc.

Inventor： Hae Rang CHOI ,  Dae Han KWON ,  Hyung Soo KIM

IPC: H03K5/15 ,  G11C7/22 ,  H03K3/037 ,  G11C7/10

CPC classification number: H03K5/15013 ,  G11C7/02 ,  G11C7/106 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  H03K3/037 ,  H03K2005/00019

Abstract: An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.

公开(公告)号：US20170031653A1

公开(公告)日：2017-02-02

申请号：US14940309

申请日：2015-11-13

Applicant: SK hynix Inc.

Inventor： Jin Ha HWANG ,  Dae Han KWON

IPC: G06F5/14 ,  G11C8/18 ,  G11C7/22

CPC classification number: G06F5/14 ,  G06F2205/126 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/4401 ,  G11C29/76

Abstract: A buffer may include a first sensing unit configured to sense data, and a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit. The buffer may include an equalization delay compensation unit configured to compensate the equalization control signals for signal processing delay times of the equalization control signals, and generate delay-compensated equalization control signals. The buffer may include a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals.

Abstract translation: 缓冲器可以包括被配置为感测数据的第一感测单元和被配置为根据第一感测单元的输出产生均衡控制信号的第二感测单元。 缓冲器可以包括均衡延迟补偿单元，其被配置为补偿均衡控制信号用于均衡控制信号的信号处理延迟时间，并且生成延迟补偿的均衡控制信号。 缓冲器可以包括噪声去除单元，其被配置为根据均衡控制信号主要消除第一感测单元的输出信号的噪声，并且二次根据延迟补偿均衡控制去除第一感测单元的输出信号的噪声 信号。

公开(公告)号：US20160218713A1

公开(公告)日：2016-07-28

申请号：US14697916

申请日：2015-04-28

Applicant: SK hynix Inc.

Inventor： Ic Su OH ,  Chang Kyu CHOI ,  Dae Han KWON

IPC: H03K19/00 ,  H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/0013 ,  H03K3/356104 ,  H03K3/35613 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/018571 ,  H03K19/018585

Abstract: A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (Tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.

Abstract translation: 公开了一种半导体器件，其涉及用于降低被配置为以高速操作发射器（Tx）的半导体芯片的电流消耗的技术。 半导体器件包括：数据驱动单元，被配置为通过根据时钟信号对输入信号进行电平移位来输出上拉驱动信号和下拉驱动信号; 以及数据输出单元，被配置为根据代码信号调整上拉驱动信号和下拉驱动信号的转换速率，并将阻抗调整信号输出到输出端子。