公开(公告)号：US20150116072A1

公开(公告)日：2015-04-30

申请号：US14517369

申请日：2014-10-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

IPC: H01H61/02 ,  H01H1/58 ,  H01H9/02

CPC classification number: H01H61/02 ,  B81B3/0021 ,  B81B2201/031 ,  B81B2203/053 ,  H01H1/58 ,  H01H9/02

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

Abstract translation: 一种装置包括容纳在集成电路的互连部分的空腔中的热变形组件。 当温度变化时，组件可以弯曲，使其自由端区垂直移位。 组件可以形成在集成电路的线路的后端。

公开(公告)号：US20140360851A1

公开(公告)日：2014-12-11

申请号：US14286331

申请日：2014-05-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

IPC: H01H59/00 ,  H01L21/822 ,  H01L27/06

CPC classification number: H01H59/0009 ,  B81B2201/018 ,  B81C1/00246 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01H1/0036 ,  H01H57/00 ,  H01H2001/0068 ,  H01H2001/0078 ,  H01H2059/0054 ,  H01L21/8221 ,  H01L23/522 ,  H01L27/0617 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes an interconnection part with several metallization levels. An electrically activatable switching device within the interconnection part has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

Abstract translation: 集成电路包括具有多个金属化级别的互连部件。 互连部件内的可电激活的开关装置具有包括由结构保持的梁的组件。 梁和结构位于相同的金属化水平内。 布置结构在梁上的固定位置，以便为梁定义位于这些固定位置之间的枢转点。 该结构在不存在电位差的情况下相对于光束和垂直于光束的平面基本对称。 在存在施加在结构的第一部分之间的第一电位差并且在存在施加在结构的第二部分之间的第二电位差的情况下在第二方向上枢转时，梁能够在第一方向上枢转。

公开(公告)号：US20140319653A1

公开(公告)日：2014-10-30

申请号：US14264227

申请日：2014-04-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/522 ,  H01G5/16 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value.

Abstract translation: 集成电路包括基板。 固定的主电容器电极设置在覆盖衬底的金属层中。 第二主电容器电极设置在金属层中并与固定主电容器电极间隔开。 可动电容电极设置在固定主电容器电极附近。 可移动电容器电极可以在可移动电容器电极和固定主电容器电极相互间隔开的第一配置之间切换，以形成电连接到主电容器的辅助电容器。 在第二构造中，可移动电容电极和固定主电容器电极以提供第二电容值的方式进行电接触。

公开(公告)号：US12057513B2

公开(公告)日：2024-08-06

申请号：US18210155

申请日：2023-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Brice Arrazat ,  Julien Delalleau ,  Joel Metz

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/94 ,  H01L49/02 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US11721773B2

公开(公告)日：2023-08-08

申请号：US17366585

申请日：2021-07-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Brice Arrazat ,  Julien Delalleau ,  Joel Metz

IPC: H01L21/00 ,  H01L29/94 ,  H01L21/28 ,  H01L21/265 ,  H01L49/02 ,  H01L29/423 ,  H01L29/788 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US10763213B2

公开(公告)日：2020-09-01

申请号：US16037595

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28 ,  H01L23/528 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11 ,  H01L29/49

Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

公开(公告)号：US10388695B2

公开(公告)日：2019-08-20

申请号：US13659622

申请日：2012-10-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L27/16 ,  H01L35/02 ,  H01L23/38 ,  H01L35/34

Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

公开(公告)号：US20190122845A1

公开(公告)日：2019-04-25

申请号：US16222017

申请日：2018-12-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio Di-Giacomo ,  Brice Arrazat

IPC: H01H61/02 ,  B81B3/00 ,  H01H1/58 ,  H01H9/02

CPC classification number: H01H61/02 ,  B81B3/0021 ,  B81B2201/031 ,  B81B2203/053 ,  H01H1/58 ,  H01H9/02

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

公开(公告)号：US20180145040A1

公开(公告)日：2018-05-24

申请号：US15596767

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/573 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/585 ,  H01L24/03 ,  H01L24/06 ,  H01L27/088

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US09899476B2

公开(公告)日：2018-02-20

申请号：US14953692

申请日：2015-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L29/06 ,  H01L29/78 ,  H01L27/112

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.