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    Semiconductor package with flexible interconnect
    33.
    发明授权
    Semiconductor package with flexible interconnect 有权

    公开(公告)号：US11542152B2

    公开(公告)日：2023-01-03

    申请号：US16934981

    申请日：2020-07-21

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Jefferson Talledo

    IPC: B81B7/00 ,  B81C1/00

    Abstract: A cavity type semiconductor package with a substrate and a cap is disclosed. The semiconductor package includes a first semiconductor die coupled to the substrate and a layer of flexible material on a surface of the cap. A trace is on the layer of flexible material. The cap is coupled to the substrate with the layer of flexible material and the trace between the cap and the substrate. A second semiconductor die is coupled to the layer of flexible material and the trace on the cap. The cap further includes an aperture to expose the second semiconductor die to the ambient environment. The layer of flexible material absorbs stress during operation cycles of the package induced by the different coefficient of thermal expansions of the cap and the substrate to reduce the likelihood of separation of the cap from the substrate.

    Semiconductor package with a cavity in a die pad for reducing voids in the solder
    34.
    发明授权
    Semiconductor package with a cavity in a die pad for reducing voids in the solder 有权

    公开(公告)号：US11133241B2

    公开(公告)日：2021-09-28

    申请号：US16910824

    申请日：2020-06-24

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Jefferson Talledo

    IPC: H01L23/495 ,  H01L23/44 ,  H01L23/48 ,  H01L21/00 ,  H01R9/00 ,  H05K5/02 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

    Abstract: A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.

    LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUFACTURING
    36.
    发明申请
    LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUFACTURING 审中-公开

    公开(公告)号：US20190074241A1

    公开(公告)日：2019-03-07

    申请号：US16174031

    申请日：2018-10-29

    Applicant: STMicroelectronics, Inc.

    Inventor： Jefferson Talledo ,  Tito Mangaoang

    IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

    Semiconductor package with individually molded leadframe and die coupled at solder balls
    37.
    发明授权
    Semiconductor package with individually molded leadframe and die coupled at solder balls 有权

    公开(公告)号：US10204814B1

    公开(公告)日：2019-02-12

    申请号：US15663624

    申请日：2017-07-28

    Applicant: STMicroelectronics, Inc.

    Inventor： Jefferson Talledo

    IPC: H01L21/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

    Abstract: According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. After the molding compound is cured, a layer of molding compound is removed to expose the solder balls. After this, a semiconductor die is electrically connected to the exposed solder balls. The combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected. The second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products.

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