公开(公告)号：US12165880B2

公开(公告)日：2024-12-10

申请号：US17550747

申请日：2021-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Michele Derai

IPC: H01L21/48 ,  H01L21/78 ,  H01L23/495

Abstract: A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.

公开(公告)号：US12142552B2

公开(公告)日：2024-11-12

申请号：US18070051

申请日：2022-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

公开(公告)号：US11626355B2

公开(公告)日：2023-04-11

申请号：US17470269

申请日：2021-09-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Michele Derai

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

公开(公告)号：US10593614B2

公开(公告)日：2020-03-17

申请号：US16398022

申请日：2019-04-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L49/02

Abstract: In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.

公开(公告)号：US10026679B2

公开(公告)日：2018-07-17

申请号：US15470494

申请日：2017-03-27

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498

Abstract: A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a supporting structure, the supporting structure being of a soluble type. A chip including a semiconductor body is mechanically coupled to the supporting structure. The sinterable material is sintered such that each preliminary contact region forms a corresponding sintered preliminary contact, and the chip and the plurality of preliminary contact regions are coated with a dielectric coating region, and the supporting structure is removed using a jet of liquid.

公开(公告)号：US20180053713A1

公开(公告)日：2018-02-22

申请号：US15471472

申请日：2017-03-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device includes: a semiconductor die having first and second opposite surfaces, a die pad having the first surface of the semiconductor die attached thereon, an electrically conductive ground pad at the second surface of the semiconductor die, a device package coupled with the semiconductor die with the ground pad lying between the semiconductor die and the package, and ground wiring or tracks for the semiconductor die between the second surface of the semiconductor die and the ground pad. A further ground connection may be provided between the ground pad at the second surface of the semiconductor die and the die pad having the semiconductor die attached thereon.

公开(公告)号：US09642244B2

公开(公告)日：2017-05-02

申请号：US13841273

申请日：2013-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana

IPC: B01L3/14 ,  H05K1/02 ,  B01L3/00 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K1/0298 ,  B01L3/502707 ,  B01L3/502715 ,  B01L2200/027 ,  B01L2200/12 ,  B01L2300/0816 ,  B01L2300/0887 ,  B01L2300/12 ,  H05K1/0272 ,  H05K1/181 ,  H05K3/30 ,  H05K2201/10083 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T137/0318

Abstract: An embodiment of a micro-electro-mechanical system of the MEMS type comprising at least one micro-electro-mechanical device of the MEMS type and one junction with a duct suitable to being associated with an external apparatus. Said junction being a printed circuit board PCB comprising at least two layers with juxtaposed faces, a channel being present in at least one face of at least one of said at least two layers suitable for realizing the duct with the juxtaposition of the other face of at least another one of at least two layers.

公开(公告)号：US09322839B2

公开(公告)日：2016-04-26

申请号：US13854782

申请日：2013-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Giulio Ricotti ,  Alberto Pagani ,  Fulvio Vittorio Fontana ,  Ubaldo Mastromatteo

IPC: G01P15/11 ,  G01P15/105 ,  G01P15/08 ,  B81B7/00 ,  B81C1/00

CPC classification number: G01P15/11 ,  B81B7/008 ,  B81B2201/025 ,  B81B2207/012 ,  B81C1/0023 ,  G01C19/5783 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

Abstract: An inertial sensor having a body with an excitation coil and a first sensing coil extending along a first axis. A suspended mass includes a magnetic-field concentrator, in a position corresponding to the excitation coil, and configured for displacing by inertia in a plane along the first axis. A supply and sensing circuit is electrically coupled to the excitation coil and to the first sensing coil, and is configured for generating a time-variable flow of electric current that flows in the excitation coil so as to generate a magnetic field that interacts with the magnetic-field concentrator to induce a voltage/current in the sensing coil. The integrated circuit is configured for measuring a value of the voltage/current induced in the first sensing coil so as to detect a quantity associated to the displacement of the suspended mass along the first axis.

Abstract translation: 惯性传感器，其具有带有激励线圈的主体和沿着第一轴线延伸的第一感测线圈。 悬挂质量体包括磁场集中器，位于对应于激励线圈的位置，并且构造成用于沿沿着第一轴线的平面中的惯性移位。 供电和感测电路电耦合到激励线圈和第一感测线圈，并且被配置为产生在励磁线圈中流动的时间流的电流，以便产生与磁场相互作用的磁场 感应线圈中的电压/电流。 集成电路被配置为测量在第一感测线圈中感应的电压/电流的值，以便检测与悬挂质量沿着第一轴的位移相关联的量。

公开(公告)号：US20150364409A1

公开(公告)日：2015-12-17

申请号：US14733209

申请日：2015-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

IPC: H01L23/498 ,  H01L21/52 ,  H01L23/367

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/52 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/18162

Abstract: An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

Abstract translation: 电子装置包括集成在模具上的电路，其具有前表面和后表面，在前表面上具有模具端子。 模具嵌入包括具有前表面和后表面的导热材料的基底的包装和通孔中。 模具在通孔中沉没。 第一绝缘材料层用模具端子的第一窗口覆盖模具前表面和封装前表面。 封装端子和封装导轨布置在第一绝缘层上。 第二绝缘材料层覆盖第一绝缘层和封装轨道，其具有用于访问封装端子的第二窗口。

公开(公告)号：US09060227B2

公开(公告)日：2015-06-16

申请号：US13659753

申请日：2012-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Alex Gritti

IPC: H01L23/552 ,  H04R19/04 ,  H04R31/00 ,  B81B7/00 ,  H04R1/02 ,  H04R1/04 ,  H04R19/00

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L2224/48091 ,  H01L2224/48137 ,  H04R1/021 ,  H04R1/04 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/029 ,  H05K9/0009 ,  H01L2924/00014

Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.

Abstract translation: 一个或多个实施例涉及封装结构，包括：具有第一表面并且容纳至少一个导电焊盘的衬底，所述至少一个导电焊盘面向第一表面延伸并且被配置为在参考电压下电耦合到导通端子; 盖构件，其设置在离基板的第一表面一定距离处; 以及在基板和盖构件之间延伸的壳体壁。 衬底，盖构件和壳体壁限定空腔，其在封装结构内部并容纳导电垫。 此外，在腔内部还存在至少一个导电结构，其在盖构件和导电垫之间延伸并与之电接触，用于将盖构件电连接到导电端子。