公开(公告)号：US20150236111A1

公开(公告)日：2015-08-20

申请号：US14683635

申请日：2015-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Hyun Lee ,  Byung-Kyu Cho ,  Jang-Hyun You ,  Albert Fayrushin

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/42364 ,  H01L21/02109 ,  H01L21/02304 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

Abstract translation: 非易失性存储器件包括栅极结构，绝缘层图案和隔离结构。 在第一方向上彼此间隔开的多个栅极结构形成在基板上。 栅结构的栅极在基本上垂直于第一方向的第二方向上延伸。 衬底包括在第二方向上交替且重复地形成的有源区和场区。 绝缘层图案形成在栅极结构之间并且其中具有第二气隙。 在每个场区域的基板上形成有在第一方向上延伸并且在栅极结构之间具有第一空气间隙，绝缘层图案和隔离结构的隔离结构。

公开(公告)号：US20140160854A1

公开(公告)日：2014-06-12

申请号：US14093717

申请日：2013-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi

IPC: H01L29/51 ,  G11C16/14 ,  G11C16/26 ,  H01L29/792 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7782 ,  H01L29/792 ,  H01L29/7923

Abstract: A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer.

Abstract translation: 非易失性存储器件包括半导体衬底和隧道绝缘层和栅电极。 具有多个层的多重隧道绝缘层，电荷存储绝缘层和具有层的多重阻挡绝缘层依次堆叠在栅电极和隧道绝缘层之间。 半导体衬底中的第一扩散区域和第二扩散区域与栅电极的相对的相对侧相邻。 当向栅电极和半导体衬底施加电压以形成其间的电压电平差时，隧道绝缘层中的最小场比阻挡绝缘层强。 阻挡绝缘层的最小电场可以比隧道绝缘层更强，通过隧道绝缘层的电荷的迁移概率可以高于通过阻挡绝缘层的迁移概率。

公开(公告)号：US20130258771A1

公开(公告)日：2013-10-03

申请号：US13790409

申请日：2013-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Hyun Lee ,  Jee-Yeon Kang ,  Dong-Hoon Jang ,  Jung-Dal Choi

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10

Abstract: In method of programming a nonvolatile memory device including first and second cell strings that are coupled to one bitline, a first channel of the first cell string and a second channel of the second cell string are precharged by applying a first voltage to the bitline, one cell string is selected from the first and second cell strings, and a memory cell included in the selected cell string is programmed by applying a second voltage greater than a ground voltage and less than the first voltage to the bitline.

Abstract translation: 在编程包括耦合到一个位线的第一和第二单元串的非易失性存储器件的方法中，通过向位线施加第一电压来预充电第一单元串的第一通道和第二单元串的第二通道，一个 从第一和第二单元串中选择单元串，并且通过向位线施加大于接地电压并小于第一电压的第二电压来对包括在所选单元串中的存储单元进行编程。

公开(公告)号：US20130100735A1

公开(公告)日：2013-04-25

申请号：US13680812

申请日：2012-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byeong-In Choe

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30

Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.

Abstract translation: 诸如NAND闪存器件的集成电路闪存器件包括常规闪存单元阵列，虚拟闪存单元阵列和擦除控制器。 擦除控制器被配置为在集成电路快闪存储器件的擦除操作期间同时向虚拟闪存单元施加不同于常规闪存单元的预定偏置电压。 还描述了相关方法。