公开(公告)号：US20230080400A1

公开(公告)日：2023-03-16

申请号：US18051034

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： KEUN HWI CHO ,  Soonmoon Jung ,  Dongwon Kim ,  Myung Gil Kang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/417 ,  H01L23/528

Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

公开(公告)号：US11257925B2

公开(公告)日：2022-02-22

申请号：US16836138

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwoo Noh ,  Munhyeon Kim ,  Hansu Oh ,  Sungman Whang ,  Dongwon Kim

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/165 ,  H01L21/311

Abstract: Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.

公开(公告)号：US11114447B2

公开(公告)日：2021-09-07

申请号：US16793912

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  TaeYong Kwon ,  Dongwon Kim

IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/092 ,  H01L29/417

Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.

公开(公告)号：US20160087026A1

公开(公告)日：2016-03-24

申请号：US14718685

申请日：2015-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Ilryong Kim ,  Changwoo Oh ,  Keun Hwi Cho ,  Toshinori Fukai

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract translation: 本发明构思的实施例提供一种电阻器和包括该电阻器的半导体器件。 电阻器包括衬底，衬底中的器件隔离层，其限定在第一方向上布置的有源区，包括从有源区垂直突出并在第一方向上彼此连接的电阻图案的电阻层，以及接触电极 电阻层。

公开(公告)号：US20240321961A1

公开(公告)日：2024-09-26

申请号：US18613338

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsu Kim ,  Myunggil Kang ,  Dongwon Kim ,  Beomjin Park ,  Inhyun Song ,  Hyumin Yoo ,  Yujin Jeon

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes, a first nano-sheet stack including a plurality of nano-sheets arranged on a fin-type active region extending in a first horizontal direction, a gate line extending in a second horizontal direction on the fin-type active region, a vertical structure contacting the plurality of nano-sheets, and a first gate dielectric layer disposed between the gate line and the plurality of nano-sheets and between the gate line and the vertical structure, wherein the gate line includes a first sub-gate portion disposed under each of the plurality of nano-sheets, the first gate dielectric layer includes a first portion disposed between the gate line and the plurality of nano-sheets, and a second portion disposed between the first sub-gate portion and the vertical structure, and a thickness of the second portion in the second horizontal direction is greater than a thickness of the first portion in the vertical direction.

公开(公告)号：US11948942B2

公开(公告)日：2024-04-02

申请号：US18122253

申请日：2023-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L29/08 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US11677029B2

公开(公告)日：2023-06-13

申请号：US17464102

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Dongwon Kim

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L29/0657 ,  H01L29/36

Abstract: A semiconductor device including an active pattern, which has a base portion and a protrusion portion on the base portion, and a source/drain pattern provided on the base portion may be provided. The protrusion portion may include a first curved pattern portion, a first flat pattern portion disposed at a lower level than the first curved pattern portion, and a second curved pattern portion disposed at a lower level than the first flat pattern portion. Each of the first and second curved pattern portions has a curved side wall, and the first flat pattern portion has a flat side wall. The germanium concentration of the first curved pattern portion is a higher than the germanium concentration of the first flat pattern portion, and the germanium concentration of the first flat pattern portion is higher than the germanium concentration of the second curved pattern portion.

公开(公告)号：US20230120496A1

公开(公告)日：2023-04-20

申请号：US18046656

申请日：2022-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunhwi Cho ,  Gibum Kim ,  Myunggil Kang ,  Dongwon Kim

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, an active fin on the substrate, and a transistor on the active fin. The transistor includes a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially stacked, and a gate structure traversing the active fin, respectively surrounding the channel layers, and including a gate dielectric and a gate electrode. The gate electrode includes a lower electrode portion between the active fin and the lower channel layer, an intermediate electrode portion between the lower channel layer and the intermediate channel layer, and an upper electrode portion between the intermediate channel layer and the upper channel layer. The gate electrode includes a work function adjusting metal element, and a content of the work function adjusting metal element in the lower electrode portion is different from that in each of the intermediate electrode portion and the upper electrode portion.

公开(公告)号：US20230051602A1

公开(公告)日：2023-02-16

申请号：US17725180

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Hyojin Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Sangmoon Lee ,  Dongwon Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.

公开(公告)号：US20220399452A1

公开(公告)日：2022-12-15

申请号：US17651623

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomjin Park ,  Myung Gil Kang ,  Dongwon Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device may include a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns, the first channel pattern including first semiconductor patterns, which are spaced apart from each other in a stacked formation, a gate electrode on the first channel pattern, a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode, and a first spacer pattern between the first gate cutting pattern and the first channel pattern. The first spacer pattern may include a first remaining pattern adjacent to an outermost side surface of at least one of the first semiconductor patterns and a second remaining pattern on the first remaining pattern. The second remaining pattern may be spaced apart from the first gate cutting pattern.