公开(公告)号：US12191136B2

公开(公告)日：2025-01-07

申请号：US18098174

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L29/74 ,  H10B12/10

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US11943925B2

公开(公告)日：2024-03-26

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Jaeho Hong ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C8/14 ,  G11C7/18 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L25/065 ,  H10B43/10

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.

公开(公告)号：US11887648B2

公开(公告)日：2024-01-30

申请号：US17362138

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: H01L29/66 ,  G11C11/39 ,  G11C11/402 ,  H01L29/749 ,  H01L27/102

CPC classification number: G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

公开(公告)号：US20230371269A1

公开(公告)日：2023-11-16

申请号：US18195522

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Kiheun Lee ,  Daewon Ha

IPC: H10B51/30 ,  H10B51/10 ,  H01L29/78 ,  H01L21/28

CPC classification number: H10B51/30 ,  H01L29/40111 ,  H01L29/78391 ,  H10B51/10

Abstract: A memory device includes a channel region, a conductive electrode on the channel region, and a data storage structure between the channel region and the conductive electrode. The data storage structure includes a stack structure including two-dimensional material layers and ferroelectric layers stacked alternately and repeatedly in a direction perpendicular to a surface of the channel region. A thickness of each of the ferroelectric layers is greater than a thickness of each of the two-dimensional material layers.

公开(公告)号：US20230163132A1

公开(公告)日：2023-05-25

申请号：US18098174

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L27/102 ,  H01L29/74

CPC classification number: H01L27/1027 ,  H01L29/742

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US20230075559A1

公开(公告)日：2023-03-09

申请号：US17741219

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

公开(公告)号：US11557720B2

公开(公告)日：2023-01-17

申请号：US17110524

申请日：2020-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Kohji Kanamori ,  Unghwan Pi ,  Hyuncheol Kim ,  Sungwon Yoo ,  Jaeho Hong

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01L23/522 ,  H01L43/02

Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.

公开(公告)号：US20220028975A1

公开(公告)日：2022-01-27

申请号：US17225716

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Sungwon Yoo ,  Jaeho Hong

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor device includes a gate electrode on a substrate, a channel surrounding sidewalls of the gate electrode on the substrate, and source/drain electrodes on the substrate at opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source/drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.