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公开(公告)号：US20230367672A1
公开(公告)日：2023-11-16
申请号：US18226622
申请日：2023-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Kijun Lee , Myungkyu Lee , Yeonggeol Song , Jinhoon Jang , Sunghye Cho , Isak Hwang
IPC: G06F11/10
CPC classification number: G06F11/1068
Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.
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公开(公告)号：US11670354B2
公开(公告)日：2023-06-06
申请号：US17408454
申请日：2021-08-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunghye Cho , Kijun Lee , Eunae Lee
IPC: G11C7/12 , G11C11/406 , G11C11/4091 , G11C11/408 , G11C7/10 , G11C8/10
CPC classification number: G11C11/406 , G11C7/12 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/40611 , G11C11/40622 , G11C7/1078 , G11C8/10
Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.
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公开(公告)号：US20230168819A1
公开(公告)日：2023-06-01
申请号：US17842981
申请日：2022-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeonggeol Song , Sungrae Kim , Kijun Lee , Myungkyu Lee , Eunae Lee , Sunghye Cho
CPC classification number: G06F3/0626 , G06F3/064 , G06F3/0679 , G06F11/1068
Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.
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公开(公告)号：US11269723B2
公开(公告)日：2022-03-08
申请号：US16988931
申请日：2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanguhn Cha , Kijun Lee , Myungkyu Lee , Sunghye Cho
Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.
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公开(公告)号：US11170868B2
公开(公告)日：2021-11-09
申请号：US16864787
申请日：2020-05-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yesin Ryu , Sanguhn Cha , Sunghye Cho , Kijun Lee , Myungkyu Lee , Youngcheon Kwon , Jaeyoun Youn
Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.
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Patent Agency Ranking
公开(公告)号：US20210208967A1
公开(公告)日：2021-07-08
申请号：US16988931
申请日：2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANGUHN CHA , Kijun Lee , Myungkyu Lee , Sunghye Cho
Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.
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公开(公告)号：US12236996B2
公开(公告)日：2025-02-25
申请号：US18197084
申请日：2023-05-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun Ae Lee , Sunghye Cho , Kijun Lee , Kyomin Sohn , Myungkyu Lee
IPC: G11C11/406
Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.
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公开(公告)号：US12066893B2
公开(公告)日：2024-08-20
申请号：US18226622
申请日：2023-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Kijun Lee , Myungkyu Lee , Yeonggeol Song , Jinhoon Jang , Sunghye Cho , Isak Hwang
CPC classification number: G06F11/1068
Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.
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公开(公告)号：US20240178861A1
公开(公告)日：2024-05-30
申请号：US18339490
申请日：2023-06-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jiho Kim , Seongmuk Kang , Daehyun Kim , Kijun Lee , Myungkyu Lee , Kyomin Sohn , Sunghye Cho
CPC classification number: H03M13/1111 , H03M13/611
Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.
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公开(公告)号：US20240096391A1
公开(公告)日：2024-03-21
申请号：US18341128
申请日：2023-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunghye Cho , Kijun Lee , Eunae Lee , Kyomin Sohn , Yeonggeol Song , Myungkyu Lee
IPC: G11C11/406
CPC classification number: G11C11/406
Abstract: A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.
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