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    MULTI-LEVEL SIGNAL RECEIVERS AND MEMORY SYSTEMS INCLUDING THE SAME
    34.
    发明申请
    MULTI-LEVEL SIGNAL RECEIVERS AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220068359A1

    公开(公告)日：2022-03-03

    申请号：US17228943

    申请日：2021-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwangseob Shin ,  Jaewoo Park ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/16

    Abstract: A multi-level signal receiver includes a data sampler having (M−1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M−1) reference voltages, to thereby generate (M−1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M−1) sense amplifiers by: (i) adjusting at least one of (M−1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M−1) reference voltages during a second training mode, based on equalized values of the (M−1) comparison signals, where each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

    ELECTRONIC DEVICES AND METHODS OF OPERATING THE SAME
    35.
    发明申请
    ELECTRONIC DEVICES AND METHODS OF OPERATING THE SAME 有权

    公开(公告)号：US20250036520A1

    公开(公告)日：2025-01-30

    申请号：US18420877

    申请日：2024-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinsoo Lim ,  Changkyu Seol ,  Myoungbo Kwak ,  Daewook Kim ,  Dongjin Park ,  Hyoungbae Ahn ,  Youngdon Choi ,  Junghwan Choi

    IPC: G06F11/10

    Abstract: An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

    Semiconductor device
    36.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12080379B2

    公开(公告)日：2024-09-03

    申请号：US17939016

    申请日：2022-09-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

    Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

    ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD
    37.
    发明公开
    ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD 审中-公开

    公开(公告)号：US20240178863A1

    公开(公告)日：2024-05-30

    申请号：US18511740

    申请日：2023-11-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinsoo Lim ,  Changkyu Seol ,  Myoungbo Kwak ,  Daewook Kim ,  Dongjin Park ,  Youngdon Choi

    IPC: H03M13/15 ,  H03M13/27 ,  H03M13/29

    CPC classification number: H03M13/1595 ,  H03M13/2778 ,  H03M13/2927

    Abstract: A device includes a receiver configured to receive a plurality of Error Correction Code (ECC) codewords transmitted from an external device through a channel including one or more lanes; an ECC decoder configured to generate a plurality of post ECC codewords by performing error correction with respect to the plurality of ECC codewords and generating a first cyclic redundancy check (CRC) codeword based on the plurality of post ECC codewords; a CRC checker configured to determine whether an error exists in the first CRC codeword; and a post ECC decoder configured to, when it is determined that the error exists in the first CRC codeword, generate a second CRC codeword by estimating a remaining error position based on error correction result information received from the ECC decoder and performing remaining error correction with respect to the plurality of post ECC codewords based on the remaining error position.

    Memory package and storage device including the same
    39.
    发明授权
    Memory package and storage device including the same 有权

    公开(公告)号：US11657860B2

    公开(公告)日：2023-05-23

    申请号：US17361780

    申请日：2021-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joohwan Kim ,  Jindo Byun ,  Younghoon Son ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C7/08 ,  G11C7/10 ,  G06F3/06 ,  G11C7/22

    CPC classification number: G11C7/1084 ,  G06F3/0656 ,  G06F3/0679 ,  G11C7/222

    Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

    DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME
    40.
    发明申请
    DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230110301A1

    公开(公告)日：2023-04-13

    申请号：US17806827

    申请日：2022-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsub Rie ,  Eunseok Shin ,  Youngdon Choi ,  Junyoung Park ,  Hyunyoon Cho ,  Junghwan Choi

    IPC: H03K5/156 ,  G11C7/22 ,  H03K3/017 ,  H03K5/135

    Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.

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