公开(公告)号：US07420202B2

公开(公告)日：2008-09-02

申请号：US11269303

申请日：2005-11-08

申请人： Vance H. Adams ,  Paul A. Grudowski ,  Venkat R. Kolagunta ,  Brian A. Winstead

发明人： Vance H. Adams ,  Paul A. Grudowski ,  Venkat R. Kolagunta ,  Brian A. Winstead

IPC分类号： H01L29/06 ,  H01L21/31

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。

公开(公告)号：US20080150072A1

公开(公告)日：2008-06-26

申请号：US11613326

申请日：2006-12-20

申请人： Brian A. Winstead ,  Vance H. Adams ,  Paul A. Grudowski

发明人： Brian A. Winstead ,  Vance H. Adams ,  Paul A. Grudowski

IPC分类号： H01L29/78

CPC分类号： H01L29/0642 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

摘要翻译： 集成电路包括包括器件的有源区的器件，其中器件的有源区包括具有横向和横向方向的沟道区。 器件还包括与有源区相邻的有源区的隔离区，该隔离区位于有源区域的横向方向，其中隔离区域包括位于与沟道区域横向的第一区域。 隔离区域还包括位于从第一区域的横向方向上的第二区域。 隔离区域的第一区域处于第一类型的应力处，并且隔离区域的第二区域是在第一类型的较小应力下或在与第一类型相反的第二类型的应力下的一个区域。

公开(公告)号：US06864135B2

公开(公告)日：2005-03-08

申请号：US10285374

申请日：2002-10-31

申请人： Paul A. Grudowski ,  Jian Chen ,  Choh-Fei Yeap

发明人： Paul A. Grudowski ,  Jian Chen ,  Choh-Fei Yeap

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/49

CPC分类号： H01L29/4983 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659

摘要： A semiconductor fabrication process is disclosed wherein a first gate (108, 114) is formed over a first portion of a semiconductor substrate (102) and a second gate (114, 108) is formed over a second portion of the substrate (102). A spacer film (118) is deposited over substrate (102) and first and second gates (108, 114). First spacers (126) are then formed on sidewalls of the second gate (114) and second spacers (136) are formed on sidewalls of first gate (108). The first and second spacers (126, 136) have different widths. The process may further include forming first source/drain regions (128) in the substrate laterally disposed on either side of the first spacers (126) and second source/drain regions (138) are formed on either side of second spacers (136). The different spacer widths may be achieved using masked first and second spacer etch processes (125, 135) having different degrees of isotropy. The spacer etch mask and the source/drain implant mask may be common such that p-channel transistors have a different spacer width than n-channel transistors.

摘要翻译： 公开了半导体制造工艺，其中第一栅极（108,114）形成在半导体衬底（102）的第一部分上，并且在衬底（102）的第二部分上方形成第二栅极（114,108）。 间隔膜（118）沉积在衬底（102）和第一和第二栅极（108,114）上。 然后在第二栅极（114）的侧壁上形成第一间隔物（126），并且第二间隔物（136）形成在第一栅极（108）的侧壁上。 第一和第二间隔物（126,136）具有不同的宽度。 该工艺可以进一步包括在横向设置在第一间隔物（126）的任一侧上的衬底中形成第一源极/漏极区（128），并且在第二间隔物（136）的任一侧上形成第二源/漏区（138）。 可以使用具有不同程度的各向同性的掩蔽的第一和第二间隔物蚀刻工艺（125,135）来实现不同的间隔物宽度。 间隔物蚀刻掩模和源极/漏极注入掩模可以是共同的，使得p沟道晶体管具有与n沟道晶体管不同的间隔物宽度。

公开(公告)号：US20140054704A1

公开(公告)日：2014-02-27

申请号：US14063459

申请日：2013-10-25

申请人： Brian A. Winstead ,  Vance H. Adams ,  Paul A. Grudowski

发明人： Brian A. Winstead ,  Vance H. Adams ,  Paul A. Grudowski

IPC分类号： H01L29/06

CPC分类号： H01L29/0642 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

摘要翻译： 集成电路包括包括器件的有源区的器件，其中器件的有源区包括具有横向和横向方向的沟道区。 器件还包括与有源区相邻的有源区的隔离区，该隔离区位于有源区域的横向方向，其中隔离区域包括位于与沟道区域横向的第一区域。 隔离区域还包括位于从第一区域的横向方向上的第二区域。 隔离区域的第一区域处于第一类型的应力处，并且隔离区域的第二区域是在第一类型的较小应力下或在与第一类型相反的第二类型的应力下。

公开(公告)号：US20110003444A1

公开(公告)日：2011-01-06

申请号：US12883096

申请日：2010-09-15

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US07714318B2

公开(公告)日：2010-05-11

申请号：US12180818

申请日：2008-07-28

申请人： Vance H. Adams ,  Paul A. Grudowski ,  Venkat R. Kolagunta ,  Brian A. Winstead

发明人： Vance H. Adams ,  Paul A. Grudowski ,  Venkat R. Kolagunta ,  Brian A. Winstead

IPC分类号： H01L29/06

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。

公开(公告)号：US07579228B2

公开(公告)日：2009-08-25

申请号：US11825953

申请日：2007-07-10

申请人： Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

发明人： Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

IPC分类号： H01L21/8238

CPC分类号： H01L21/823468 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3146 ,  H01L21/823864 ,  H01L29/6653 ,  Y10S438/943

摘要： A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

摘要翻译： 提供一种制造半导体器件的方法，包括（a）提供包括第一栅电极（210）的半导体结构; （b）形成与所述第一电极相邻的第一组有机间隔物（213）; （c）在所述结构上沉积第一光掩模（215）; 和（d）同时去除第一组有机间隔物和第一光掩模。

公开(公告)号：US07511360B2

公开(公告)日：2009-03-31

申请号：US11300091

申请日：2005-12-14

申请人： Mehul D. Shroff ,  Paul A. Grudowski

发明人： Mehul D. Shroff ,  Paul A. Grudowski

IPC分类号： H01L29/72

CPC分类号： H01L29/7843 ,  H01L21/3185 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.

摘要翻译： 通过在其上分别施加拉伸和压缩的应力层来增强N沟道和P沟道晶体管。 发现关于两个应力层的以前未知的问题，这两个应力层都可以方便地是氮化的，但是略有不同。 两个应力源具有不同的蚀刻速率，这在蚀刻两个应激物之间的界面处的接触孔时会产生有害影响。 与栅极的接触通常优选在N沟道晶体管和P沟道晶体管之间，这也是两个应力层之间边界的看似最佳位置。 在边界处的接触蚀刻可导致底层栅极结构或接触孔中的残余氮化物的点蚀。 因此，已经发现有益的是确保每个接触件与来自接触件通过的相反类型的应力器至少一定的距离。

公开(公告)号：US07491630B2

公开(公告)日：2009-02-17

申请号：US11375768

申请日：2006-03-15

申请人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

发明人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

IPC分类号： H01L21/04

CPC分类号： H01L21/82345 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462

摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.

摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的本征多晶硅层（26），从而形成具有垂直侧壁轮廓（61,63）的蚀刻栅极（62,64）。 虽然本征多晶硅层（26）的覆盖氮氮注入（46）可以在栅极蚀刻之前发生，但是在源极/漏极中通过完全掺杂栅极（80,100）来获得更理想化的垂直栅极侧壁轮廓（61,63） 漏极注入步骤（71,77,91,97）和栅极蚀刻之后。

公开(公告)号：US20090017587A1

公开(公告)日：2009-01-15

申请号：US11825953

申请日：2007-07-10

申请人： Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

发明人： Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

IPC分类号： H01L21/8238

CPC分类号： H01L21/823468 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3146 ,  H01L21/823864 ,  H01L29/6653 ,  Y10S438/943

摘要： A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.