公开(公告)号：US5824365A

公开(公告)日：1998-10-20

申请号：US668855

申请日：1996-06-24

申请人： Gurtej S. Sandhu ,  Ravi Iyer ,  Donald L. Westmoreland

发明人： Gurtej S. Sandhu ,  Ravi Iyer ,  Donald L. Westmoreland

IPC分类号： C23C16/44 ,  B05D7/22 ,  C23C16/00

CPC分类号： C23C16/4404

摘要： A method of inhibiting deposition of material on a wall of a chemical vapor deposition reactor includes providing a chemical vapor deposition reactor having a wall which has an inside facing surface, the inside facing surface at least partially defining a chemical vapor deposition reactor chamber; forming a first material atop the inside facing surface; positioning a substrate in the chemical vapor deposition reactor chamber, the substrate having an outer surface; and chemical vapor depositing a second material layer on the substrate in a manner which is selective to the substrate outer surface, and not the first material, thereby restricting deposition of the second layer on the reactor inside facing surface.

摘要翻译： 一种抑制材料沉积在化学气相沉积反应器的壁上的方法包括提供具有壁的化学气相沉积反应器，所述壁具有面向内的表面，所述内表面至少部分地限定化学气相沉积反应室; 在面向内表面的顶部形成第一材料; 将衬底定位在化学气相沉积反应器室中，所述衬底具有外表面; 以及以对衬底外表面有选择性的方式在衬底上沉积第二材料层，而不是第一材料，由此限制第二层在反应器面对表面上的沉积。

公开(公告)号：US08202806B2

公开(公告)日：2012-06-19

申请号：US11242375

申请日：2005-10-03

申请人： Randhir P.S. Thakur ,  Ravi Iyer ,  Howard Rhodes

发明人： Randhir P.S. Thakur ,  Ravi Iyer ,  Howard Rhodes

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/3171 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

摘要翻译： 提供了一种制造具有降低的阈值电压偏移的集成电路的方法。 在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。 有源区由非导电区分开。 势垒层和电介质层沉积在非导电区域上并在有源区上方。 对集成电路施加热量，导致阻挡层退火。

公开(公告)号：US20110090920A1

公开(公告)日：2011-04-21

申请号：US12980682

申请日：2010-12-29

申请人： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

发明人： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

IPC分类号： H04L12/66

CPC分类号： H04L45/74 ,  H04L49/20 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166

摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

摘要翻译： 一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段 协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。 该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷 。 该方法还包括产生导致因特网协议分组的接收处理的信号。

公开(公告)号：US20100285238A1

公开(公告)日：2010-11-11

申请号：US12843518

申请日：2010-07-26

申请人： Gurtej S. Sandhu ,  Ravi Iyer

发明人： Gurtej S. Sandhu ,  Ravi Iyer

IPC分类号： C23C16/48

CPC分类号： C23C16/401

摘要： Disclosed is a deposition process for forming a glass film. An embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the gases above the substrate surface to a high intensity light source.

摘要翻译： 公开了一种用于形成玻璃膜的沉积工艺。 一种实施方案，其包括以下步骤：在化学气相沉积室中设置衬底，并在臭氧存在下将衬底表面暴露于SiO 2前体气体，载体气体和任选的掺杂气体，并将气体的反应体积暴露于高于 衬底表面到高强度光源。

公开(公告)号：US20090194818A1

公开(公告)日：2009-08-06

申请号：US12424455

申请日：2009-04-15

申请人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

发明人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

IPC分类号： H01L27/092

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/78

摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

摘要翻译： 晶体管栅极形成方法包括形成第一和第二晶体管栅极。 两个栅极中的每一个包括下金属层和上金属层。 第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现出的功函数相同的功函数的沉积材料。 然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。 第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

公开(公告)号：US07545009B2

公开(公告)日：2009-06-09

申请号：US11072159

申请日：2005-03-04

申请人： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

发明人： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

IPC分类号： H01L29/78

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

摘要翻译： 使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。 每种难熔金属材料是含有难熔金属和杂质的导电材料。 第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。 与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。 因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。 这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

公开(公告)号：US20060030162A1

公开(公告)日：2006-02-09

申请号：US11242375

申请日：2005-10-03

申请人： Randhir Thakur ,  Ravi Iyer ,  Howard Rhodes

发明人： Randhir Thakur ,  Ravi Iyer ,  Howard Rhodes

IPC分类号： H01L21/469

CPC分类号： H01L23/3171 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

公开(公告)号：US20050161721A1

公开(公告)日：2005-07-28

申请号：US11072159

申请日：2005-03-04

申请人： Ravi Iyer ,  Yongjun Hu ,  Luan Tran ,  Brent Gilgen

发明人： Ravi Iyer ,  Yongjun Hu ,  Luan Tran ,  Brent Gilgen

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/45 ,  H01L27/108

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

摘要翻译： 使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。 每种难熔金属材料是含有难熔金属和杂质的导电材料。 第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。 与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。 因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。 这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

公开(公告)号：US06864561B2

公开(公告)日：2005-03-08

申请号：US10727889

申请日：2003-12-04

申请人： Ravi Iyer ,  Randhir P. S. Thakur ,  Howard E. Rhodes

发明人： Ravi Iyer ,  Randhir P. S. Thakur ,  Howard E. Rhodes

IPC分类号： H01L21/316 ,  H01L23/58 ,  H01L21/31

CPC分类号： H01L21/02164 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625

摘要： The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

摘要翻译： 通过使诸如TEOS的有机前体与O 3反应，沉积在半导体器件上的硼磷硅玻璃绝缘膜中的固定电荷被还原。 当在高于约480摄氏度的温度下完成时，所得膜中的碳水平似乎降低，导致场晶体管器件的阈值电压更高。

公开(公告)号：US06822303B2

公开(公告)日：2004-11-23

申请号：US10400010

申请日：2003-03-26

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L2994

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/76895

摘要： A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.

摘要翻译： 用于制造栅电极的方法包括提供栅极氧化层并在氧化物层上形成硼化钛层。 在硼化钛层上形成绝缘体盖层，之后，由硼化钛层形成栅电极。 在形成硼化钛层之前，可以在氧化物层上形成阻挡层，其中栅电极由阻挡层和硼化钛层形成。 此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层，其中栅电极由硼化钛层和多晶硅层形成。 此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层和在多晶硅层上形成的势垒层。 然后，由多晶硅层，阻挡层和硼化钛层形成栅电极。 类似的方法可以进一步用于形成互连以连接接触区域。 还描述了由该方法产生的栅电极结构和互连结构。 此外，在这些方法和结构中，硼化钛层可以是二硼化钛层或其中掺入硅的硼化钛层。