公开(公告)号：US08089128B2

公开(公告)日：2012-01-03

申请号：US12424455

申请日：2009-04-15

申请人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

发明人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

IPC分类号： H01L27/092

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/78

摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

摘要翻译： 晶体管栅极形成方法包括形成第一和第二晶体管栅极。 两个栅极中的每一个包括下金属层和上金属层。 第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现的功函数相同的功函数的沉积材料。 然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。 第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

公开(公告)号：US07538001B2

公开(公告)日：2009-05-26

申请号：US11219079

申请日：2005-09-01

申请人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

发明人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

IPC分类号： H01L21/00

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/78

摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

摘要翻译： 晶体管栅极形成方法包括形成第一和第二晶体管栅极。 两个栅极中的每一个包括下金属层和上金属层。 第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现出的功函数相同的功函数的沉积材料。 然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现出的功函数不同的修正功函数。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。 第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

公开(公告)号：US20090194818A1

公开(公告)日：2009-08-06

申请号：US12424455

申请日：2009-04-15

申请人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

发明人： D. V. Nirmal Ramaswamy ,  Ravi Iyer

IPC分类号： H01L27/092

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/78

摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

摘要翻译： 晶体管栅极形成方法包括形成第一和第二晶体管栅极。 两个栅极中的每一个包括下金属层和上金属层。 第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现出的功函数相同的功函数的沉积材料。 然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。 与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。 第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

公开(公告)号：US09142767B2

公开(公告)日：2015-09-22

申请号：US13234875

申请日：2011-09-16

申请人： David H. Wells ,  D. V. Nirmal Ramaswamy ,  Kirk D. Prall

发明人： David H. Wells ,  D. V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/085 ,  G11C2213/73 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

摘要： Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.

摘要翻译： 包括集成选择装置和存储元件的电阻式存储单元及其形成方法在此描述。 作为示例，电阻式存储单元可以包括包括肖特基接口的选择器件结构和与选择器件结构集成的存储元件，使得对应于肖特基界面的电极用作存储元件的第一电极。 存储元件可以包括形成在第一电极和第二电极之间的存储材料。

公开(公告)号：US08351242B2

公开(公告)日：2013-01-08

申请号：US12893992

申请日：2010-09-29

申请人： D. V. Nirmal Ramaswamy ,  Kirk D. Prall

发明人： D. V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC分类号： G11C11/00 ,  G11C11/34 ,  H01L27/105

CPC分类号： H01L45/14 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

摘要： Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

公开(公告)号：US20130001673A1

公开(公告)日：2013-01-03

申请号：US13615030

申请日：2012-09-13

申请人： D. V. Nirmal Ramaswamy ,  Matthew N. Rocklein ,  Rhett Brewer

发明人： D. V. Nirmal Ramaswamy ,  Matthew N. Rocklein ,  Rhett Brewer

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L21/314 ,  B82Y40/00

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  G11C11/5671 ,  H01L21/02148 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/42348

摘要： Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.

摘要翻译： 公开了用于形成存储器单元的存储器，系统和方法。 一个这种存储单元包括电荷存储节点，其在隧道电介质上方包括纳米点，并且在纳米点上包括保护膜。 在另一个存储单元中，电荷存储节点包括包含钌合金的纳米点。 存储单元可以包括在保护膜或钌合金纳米点上的栅极间电介质和在栅极间电介质上的控制栅极。 保护膜和钌合金可以被配置为在形成栅极间电介质期间保护至少一些纳米点不被蒸发。

公开(公告)号：US07968406B2

公开(公告)日：2011-06-28

申请号：US12351099

申请日：2009-01-09

申请人： D. V. Nirmal Ramaswamy ,  Noel Rocklein ,  Kyu S. Min

发明人： D. V. Nirmal Ramaswamy ,  Noel Rocklein ,  Kyu S. Min

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

摘要翻译： 一些实施例包括存储器单元。 存储单元可以包括隧道电介质材料，隧道电介质材料上方的电荷保持区域，电荷保持区域上的结晶超高k电介质材料，以及结晶超高k电介质材料上的控制栅极材料。 此外，存储器单元可以包括电荷保持区域和结晶超高k电介质材料之间的非晶区域，和/或可以包括晶体超高k电介质材料和控制栅极材料之间的非晶区域。 一些实施例包括形成在电荷保持区域和结晶超高k电介质材料之间形成非晶区域的存储单元的方法，和/或在晶体超高k电介质材料和控制栅极之间包含非晶区域的方法 材料。

公开(公告)号：US07667260B2

公开(公告)日：2010-02-23

申请号：US11501525

申请日：2006-08-09

申请人： Gurtej S. Sandhu ,  D. V. Nirmal Ramaswamy

发明人： Gurtej S. Sandhu ,  D. V. Nirmal Ramaswamy

IPC分类号： H01L21/336 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L29/788 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S977/721 ,  Y10S977/762

摘要： A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

摘要翻译： 提供了包括覆盖在半导体衬底上的隧道电介质层的存储单元。 存储单元还包括具有覆盖隧道介电层的第一部分的浮动栅极和从第一部分延伸的纳米棒形式的第二部分。 此外，控制栅极层通过隔间电介质层与浮置栅极分离。

公开(公告)号：US09196753B2

公开(公告)日：2015-11-24

申请号：US13089648

申请日：2011-04-19

申请人： D. V. Nirmal Ramaswamy ,  Gurtej Sandhu

发明人： D. V. Nirmal Ramaswamy ,  Gurtej Sandhu

IPC分类号： H01L27/108 ,  H01L29/872 ,  H01L27/28 ,  H01L45/00 ,  H01L27/102 ,  H01L29/885 ,  H01L27/22 ,  H01L27/24 ,  G11C11/56 ,  G11C13/00

CPC分类号： H01L29/872 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/285 ,  H01L29/885 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (Å) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.

摘要翻译： 为选择装置提供方法，装置和系统，所述选择装置可以包括形成在第一电极上的至少一个半导体材料的半导体叠层，其中半导体叠层可以具有约700埃（或更小）的厚度。 所述至少一个半导体材料中的每一个可以具有约4电子伏（eV）或更小的相关带隙，并且可以在半导体叠层上形成第二电极。

公开(公告)号：US09136306B2

公开(公告)日：2015-09-15

申请号：US13340375

申请日：2011-12-29

申请人： D. V. Nirmal Ramaswamy ,  Mark S. Korber

发明人： D. V. Nirmal Ramaswamy ,  Mark S. Korber

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2463 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2418 ,  H01L29/456 ,  H01L29/861 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666 ,  H01L45/1683

摘要： Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.

摘要翻译： 一些实施例包括在存储器单元上具有二极管的存储器结构。 存储单元可以包括一对电极之间的可编程材料，可编程材料直接与高k电介质一起包含多价金属氧化物。 二极管可以包括直接在一个存储单元电极上并与存储单元电极电耦合的第一二极管电极，并且可以包括在第一二极管电极的横向外部并且不直接在存储单元上方的第二二极管电极。 一些实施例包括包括存储器结构的存储器阵列，并且一些实施例包括制造存储器结构的方法。