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    Dynamic random access memory circuit array and memory cell
    31.
    发明授权
    Dynamic random access memory circuit array and memory cell 失效
    动态随机存取存储器电路阵列和存储单元

    公开(公告)号：US5834805A

    公开(公告)日：1998-11-10

    申请号：US717015

    申请日：1996-09-20

    申请人： Sanh Tang

    发明人： Sanh Tang

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76

    CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/1203 ,  H01L28/40

    摘要： A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor container openings with insulative material; j) providing a gate dielectric layer atop the SOI layer islands; k) providing conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; 1) providing opposing FET source and drain regions within the SOI layer; and m) providing bit lines outwardly of the word lines, the bit lines connecting with selected drain regions. Also contemplated is a DRAM array having sources and drains formed within an SOI layer, wherein capacitors of the array comprise trenches formed within a monocrystalline substrate, with the substrate comprising a common cell plate of the capacitors.

    摘要翻译： 形成动态随机存取存储器电路的半导体处理方法包括：a）提供导电电容器单元板基板; b）在电池板上提供电绝缘层; c）在绝缘层上提供半导体材料层，从而限定绝缘体上半导体（SOI）层; d）图案化和蚀刻SOI层以限定岛之间的有源区域岛和隔离沟槽; e）用绝缘材料填充隔离沟; f）提供通过SOI层和绝缘层的电容器开口进入电池板衬底; g）在电容器开口内的电池板衬底上提供电容器电介质层; h）在电容器开口内的电介质层上提供相应的电容器存储节点，各个存储节点与SOI层欧姆连接; i）在提供存储节点之后，用绝缘材料填充电容器容器开口的剩余部分; j）在SOI层岛顶上提供栅介质层; k）在岛上的栅极电介质层和填充的隔离沟槽之上提供导电字线; 1）在SOI层内提供相对的FET源极和漏极区域; 并且m）在字线外部提供位线，位线与选择的漏极区域连接。 还考虑了具有形成在SOI层内的源极和漏极的DRAM阵列，其中阵列的电容器包括形成在单晶衬底内的沟槽，衬底包括电容器的公共电池板。

    Integrated circuitry with interconnection pillar
    32.
    发明授权
    Integrated circuitry with interconnection pillar 失效
    具有互连柱的集成电路

    公开(公告)号：US5701036A

    公开(公告)日：1997-12-23

    申请号：US672305

    申请日：1996-06-27

    申请人： Sanh Tang

    发明人： Sanh Tang

    IPC分类号： H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L23/485 ,  H01L27/04 ,  H01L29/417 ,  H01L23/48 ,  H01L23/52 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/417 ,  H01L21/76885 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/903 ,  Y10S438/97 ,  H01L2924/00

    摘要： A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which connects with the base region through the second layer plug; and h) etching unmasked portions of the first layer and second layer plug to define a circuit component which connects with the base region through the second layer plug, the greater thickness of the second layer plug as compared to the thickness of the first layer restricting etching into the base region during etching. Integrated circuitry is also disclosed.

    摘要翻译： 半导体处理方法包括：a）提供具有要与其进行电连接的基极区域的基板; b）提供第一层导电第一材料; c）在第一层上提供蚀刻停止层; d）通过蚀刻停止层和第一层蚀刻到基底区域的接触开口; e）在所述蚀刻停止层的外部和所述接触开口内提供第二层第一材料，其厚度大于所述第一层厚度并向外延伸超出所述接触开口上边缘; f）去除第二层的第一材料并在接触件内限定第二层塞，第二层塞具有向外延伸超过接触开口上边缘的最外表面，从而使第二层塞具有比第一层 层; g）从第一层和第二层插塞向外掩蔽，以限定掩模图案，用于定义来自第一层的电路部件，该第一层通过第二层插塞与基部区域连接; 以及h）蚀刻所述第一层和第二层插塞的未屏蔽部分以限定通过所述第二层插塞与所述基底区域连接的电路部件，所述第二层插塞的厚度与所述第一层限制蚀刻的厚度相比较大 在蚀刻期间进入基底区域。 还公开了集成电路。

    Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer
    33.
    发明授权
    Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer 失效
    在外层和内层之间形成电互连的半导体加工方法

    公开(公告)号：US5506172A

    公开(公告)日：1996-04-09

    申请号：US298209

    申请日：1994-08-29

    申请人： Sanh Tang

    发明人： Sanh Tang

    IPC分类号： H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L23/485 ,  H01L27/04 ,  H01L29/417 ,  H01L21/44

    CPC分类号： H01L29/417 ,  H01L21/76885 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/903 ,  Y10S438/97

    摘要： A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which connects with the base region through the second layer plug; and h) etching unmasked portions of the first layer and second layer plug to define a circuit component which connects with the base region through the second layer plug, the greater thickness of the second layer plug as compared to the thickness of the first layer restricting etching into the base region during etching.

    摘要翻译： 半导体处理方法包括：a）提供具有要与其进行电连接的基极区域的基板; b）提供第一层导电第一材料; c）在第一层上提供蚀刻停止层; d）通过蚀刻停止层和第一层蚀刻到基底区域的接触开口; e）在所述蚀刻停止层的外部和所述接触开口内提供第二层第一材料，其厚度大于所述第一层厚度并向外延伸超出所述接触开口上边缘; f）去除第二层的第一材料并在接触件内限定第二层塞，第二层塞具有向外延伸超过接触开口上边缘的最外表面，从而使第二层塞具有比第一层 层; g）从第一层和第二层插塞向外掩蔽，以限定掩模图案，用于定义来自第一层的电路部件，该第一层通过第二层插塞与基部区域连接; 以及h）蚀刻所述第一层和第二层插塞的未屏蔽部分以限定通过所述第二层插塞与所述基底区域连接的电路部件，所述第二层插塞的厚度与所述第一层限制蚀刻的厚度相比较大 在蚀刻期间进入基底区域。

    Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions
    35.
    发明申请
    Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions 有权
    浮体晶体管结构，半导体结构和形成半导体结构的方法

    公开(公告)号：US20070252175A1

    公开(公告)日：2007-11-01

    申请号：US11393513

    申请日：2006-03-29

    申请人： Sanh Tang ,  Venkatesan Ananthan

    发明人： Sanh Tang ,  Venkatesan Ananthan

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7827 ,  H01L29/7841

    摘要： The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.

    摘要翻译： 本发明包括含有U形半导体材料片的浮体晶体管结构。 U形有一对连接到中心部分的插脚。 每个插脚包含一对门控耦合的源极/漏极区域的源极/漏极区域，并且晶体管的浮体在中心部分内。 半导体材料切片可以位于前门和后门之间。 可以将浮体晶体管结构并入到存储器阵列中，这又可以并入到电子系统中。 本发明还包括形成浮体晶体管结构的方法，以及将浮体晶体管结构结合到存储器阵列中的方法。

    Transistor gate forming methods and transistor structures
    36.
    发明申请
    Transistor gate forming methods and transistor structures 有权
    晶体管栅极形成方法和晶体管结构

    公开(公告)号：US20070166920A1

    公开(公告)日：2007-07-19

    申请号：US11716433

    申请日：2007-03-08

    申请人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

    发明人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

    摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

    摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。

    Cross diffusion barrier layer in gate structure
    38.
    发明申请
    Cross diffusion barrier layer in gate structure 审中-公开
    栅极结构中的交叉扩散阻挡层

    公开(公告)号：US20070102753A1

    公开(公告)日：2007-05-10

    申请号：US11646896

    申请日：2006-12-28

    申请人： Sanh Tang ,  Chih-Chen Cho ,  Robert Burke ,  Anuradha Iyengar ,  Eugene Gifford

    发明人： Sanh Tang ,  Chih-Chen Cho ,  Robert Burke ,  Anuradha Iyengar ,  Eugene Gifford

    IPC分类号： H01L29/788 ,  H01L29/76

    CPC分类号： H01L27/11 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/4941 ,  Y10S257/903 ,  Y10S438/927

    摘要： Various embodiments include a substrate having including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate, an insulation layer overlying the substrate, a gate layer overlying the insulation layer, a barrier layer overlying the gate layer, and an electrode layer overlying the barrier layer. The first and third doped regions may be located on a first side of the gate layer. The second and fourth doped regions may be located on a second side of the gate layer. The first and third doped regions may be source and drain regions of a first transistor. The second and fourth doped regions may be source and drain regions of a second transistor. The gate layer may include a gate segment to couple to a third transistor. Other embodiments are disclosed.

    摘要翻译： 各种实施例包括具有第一掺杂区域和位于衬底第一侧上的第二掺杂区域的衬底，以及位于衬底第二侧上的第三掺杂区域和第四掺杂区域，覆盖衬底的绝缘层 ，覆盖绝缘层的栅极层，覆盖栅极层的势垒层和覆盖阻挡层的电极层。 第一和第三掺杂区域可以位于栅极层的第一侧上。 第二和第四掺杂区域可以位于栅极层的第二侧上。 第一和第三掺杂区可以是第一晶体管的源区和漏区。 第二和第四掺杂区可以是第二晶体管的源区和漏区。 栅极层可以包括耦合到第三晶体管的栅极段。 公开了其他实施例。

    Transistor gate forming methods and transistor structures
    39.
    发明申请
    Transistor gate forming methods and transistor structures 有权

    公开(公告)号：US20070048941A1

    公开(公告)日：2007-03-01

    申请号：US11219077

    申请日：2005-09-01

    申请人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

    发明人： Sanh Tang ,  Gordon Haller ,  Prashant Raghu ,  Ravi Iyer

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

    摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.