公开(公告)号：US06699743B2

公开(公告)日：2004-03-02

申请号：US10198215

申请日：2002-07-17

申请人： John T. Moore ,  Mark Fischer

发明人： John T. Moore ,  Mark Fischer

IPC分类号： H01L218238

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/3115 ,  H01L21/3144 ,  H01L21/823462 ,  H01L29/518 ,  H01L29/78

摘要： The present invention provides a method for fabricating improved integrated circuit devices. The method of the present invention enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected. The method of the present invention is extremely adaptable and may further include additional thermal oxidation steps used to thicken non-hardened portions of the gate oxide layer, as well as additional masking, and hardening steps, which may provide multiple hardened or non-hardened portions of varying thicknesses within a single gate oxide layer. Thus, the method of the present invention may be used to fabricate an IC device having selectively hardened N-channel and P-channel devices having gate oxides of varying thickness.

摘要翻译： 本发明提供一种制造改进的集成电路器件的方法。 本发明的方法能够选择性地硬化栅极氧化物层，并且包括提供其上形成有栅氧化层的半导体衬底。 然后在栅极氧化物层上形成抗蚀剂，并将其图案化以暴露待硬化的栅极氧化物层的一个或多个区域。 然后使用真正的远程等离子体氮化（RPN）方案或高密度等离子体（HDP）RPN方案来硬化栅极氧化物层的暴露部分。 由于本发明方法中使用的RPN方案在低温下运行，图案化的抗蚀剂通过RPN工艺保持稳定，并且由图案化的抗蚀剂暴露的那些栅极氧化物层的那些区域通过RPN处理选择性硬化，而 由图案化的抗蚀剂覆盖的区域保持不受影响。 本发明的方法是非常适用的，并且还可以包括用于增厚栅极氧化物层的非硬化部分的额外的热氧化步骤，以及额外的掩蔽和硬化步骤，其可以提供多个硬化或非硬化部分 在单个栅极氧化物层内具有变化的厚度。 因此，本发明的方法可用于制造具有选择性硬化的具有不同厚度的栅极氧化物的N沟道和P沟道器件的IC器件。

公开(公告)号：US06461985B1

公开(公告)日：2002-10-08

申请号：US09393542

申请日：1999-09-10

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  H01L21/32 ,  H01L21/76202

摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

公开(公告)号：US06300671B1

公开(公告)日：2001-10-09

申请号：US09376886

申请日：1999-08-18

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L2358

CPC分类号： H01L21/31144 ,  G03F7/091 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/312

摘要： In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.

摘要翻译： 一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上形成光致抗蚀剂。 另一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; c）在阻挡层上形成光致抗蚀剂; d）将所述光致抗蚀剂暴露于图案化的光束以使所述光致抗蚀剂的至少一部分在溶剂中比其它部分更易溶，所述阻挡层是吸收通过所述光致抗蚀剂的光的抗反射表面; 以及e）将所述光致抗蚀剂暴露于所述溶剂以除去所述至少一个部分，同时将所述另一部分留在所述阻挡层上。 在另一方面，本发明包括半导体晶片组件，包括：a）氮化硅材料，该材料具有表面; b）在所述材料的表面上的阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上并抵靠所述阻挡层的光致抗蚀剂。

公开(公告)号：US6093956A

公开(公告)日：2000-07-25

申请号：US100530

申请日：1998-06-18

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L29/76 ,  H01L23/16

CPC分类号： H01L21/3185 ,  H01L21/32 ,  H01L21/76202

摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of the at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

摘要翻译： 一方面，本发明包括一种半导体晶片处理方法，包括在半导体晶片的表面上形成氮化硅层，所述氮化硅层包括至少两个部分，所述至少两个部分中的一个部分产生抵抗 所述至少两个部分中的另一个，并且所述至少两个部分中的另一部分产生相对于所述至少两个部分中的一个部分的张力。 在另一方面，本发明包括减少半导体晶片上的应力的方法，该半导体晶片具有一对相对的表面，并且在相对表面的一个之上具有比另一个相对表面更多的氮化硅，该方法包括提供 所述相对表面中的一个上的氮化硅包括第一部分，第二部分和第三部分，所述第一部分，第二部分和第三部分相对于彼此正向移位，所述第二部分位于第一部分和第三部分之间， 第二部分具有比第一和第三部分更大的化学计算量的硅，与相对表面上的一个相反的表面上的氮化硅在整个厚度上具有恒定的化学计量的硅时，半导体晶片受到的应力较小。 在另一方面，本发明包括半导体晶片组件。

公开(公告)号：US08058130B2

公开(公告)日：2011-11-15

申请号：US12196988

申请日：2008-08-22

申请人： Gurtej S. Sandhu ,  John T. Moore ,  Neal R. Rueger

发明人： Gurtej S. Sandhu ,  John T. Moore ,  Neal R. Rueger

IPC分类号： H01L21/00

CPC分类号： H01L21/02332 ,  H01L21/0234 ,  H01L21/265 ,  H01L21/28061 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.

摘要翻译： 本发明包括将氮掺入含氧化硅的层中的方法。 将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。 氮气随后在层内热退火以将至少一些氮与硅结合在层内。 本发明还包括形成晶体管的方法。 在半导体衬底上形成栅氧化层。 栅氧化层包括二氧化硅。 将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。 随后，层内的氮被热退火以将至少大部分氮与硅结合。 在栅极氧化物层上形成至少一个导电层。 源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。 本发明还包括晶体管结构。

公开(公告)号：US20080225579A1

公开(公告)日：2008-09-18

申请号：US12110532

申请日：2008-04-28

申请人： John T. Moore ,  Terry L. Gilton

发明人： John T. Moore ,  Terry L. Gilton

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00 ,  H01L21/00

CPC分类号： G11C13/003 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0011 ,  G11C13/004 ,  G11C2213/75 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052

摘要： An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a bit line through respective first electrodes and access transistors controlled by respective word lines. The memory elements each have a respective second electrode coupled thereto which in cooperation with the bit line access transistors and first electrode, serves to apply read, write and erase signals to the memory element.

摘要翻译： 一种架构及其形成和操作方法，其包含半易失性或非易失性存储器元件的高密度存储器阵列，包括但不限于可编程导电存取存储器元件。 一个示例性实施例中的架构具有一对半挥发性或非易失性存储器元件，其通过相应的第一电极和由相应字线控制的存取晶体管选择性地共享位线。 存储元件各自具有耦合到其上的相应的第二电极，其与位线存取晶体管和第一电极协作，用于向存储元件施加读取，写入和擦除信号。

公开(公告)号：US07385868B2

公开(公告)日：2008-06-10

申请号：US11128177

申请日：2005-05-13

申请人： John T. Moore ,  Terry L. Gilton ,  Kristy A. Campbell

发明人： John T. Moore ,  Terry L. Gilton ,  Kristy A. Campbell

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/406 ,  G11C11/40622 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0033 ,  G11C16/3431 ,  G11C2211/4065 ,  G11C2211/4068 ,  G11C2213/79

摘要： A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of discrete refresh voltages to the PCRAM cells in an array. Specifically, the array structure of a PCRAM device is constructed to allow leakage current to flow through each programmed cell in the array to refresh the programmed state. In one embodiment, the leakage current flows across the access device between the anode of the memory element and the bit line to which the cell is connected, for each memory cell in the array which has been programmed to the low resistance state. In another embodiment, the leakage current flows to the programmed cells through a doped substrate or doped regions of a substrate on which each cell is formed. An entire array is refreshed simultaneously by forming each memory element in the array to have one common anode formed as a single cell plate for the array. Only PCRAM cells in the array written to the low resistance state are refreshed by the controlled leakage current, whereas cells in the high resistance state are not affected by the refresh operation.

摘要翻译： 用于刷新编程为低电阻状态的PCRAM细胞的方法和PCRAM细胞的整个阵列使用简单的刷新方案，其不需要单独控制并且向阵列中的PCRAM细胞施加离散的刷新电压。 具体地，构建PCRAM器件的阵列结构以允许漏电流流过阵列中的每个编程单元以刷新编程状态。 在一个实施例中，针对已经被编程为低电阻状态的阵列中的每个存储器单元，漏电流在存储元件的阳极和单元连接的位线之间流过访问设备。 在另一个实施例中，漏电流通过其上形成有每个单元的衬底的掺杂衬底或掺杂区流动到编程单元。 通过在阵列中形成每个存储元件以使一个共同的阳极形成为阵列的单个单元板，整个阵列同时刷新。 写入低电阻状态的阵列中只有PCRAM单元被控制的漏电流刷新，而高电阻状态下的单元不受刷新操作的影响。

公开(公告)号：US07199444B2

公开(公告)日：2007-04-03

申请号：US11219742

申请日：2005-09-07

申请人： John T. Moore ,  Terry L. Gilton

发明人： John T. Moore ,  Terry L. Gilton

IPC分类号： H01L29/12

CPC分类号： H01L45/04 ,  H01L27/101 ,  H01L28/24 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1658 ,  H01L45/1675

摘要： A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices. In one implementation, a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure includes a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material. At least one of the electrodes has a conductive projection extending into the resistance variable chalcogenide material.

摘要翻译： 金属掺杂硫族化物材料的方法包括在衬底上形成金属。 在金属上形成硫族化物材料。 通过硫属化物材料对金属进行辐射，有效地在金属和硫族化物材料的界面处破坏硫族化物材料的硫族化物键，并将至少一些金属向外扩散到硫族化物材料中。 金属掺杂硫族化物材料的方法包括用硫族化物材料包围突出的金属块的暴露的外表面。 通过硫族化物材料将辐射照射到突出金属质量块上，有效地在突出的金属质量外表面的界面处破坏硫族化物材料的硫族化物键，并将至少一些突出的金属块向外扩散到硫族化物材料中。 在某些方面，上述实施方式被并入形成非易失性电阻可变器件的方法中。 在一个实施方案中，对于给定的环境温度和压力，最高电阻状态的非易失性电阻可变器件包括在其中扩散有金属离子的电阻变化硫属化物材料。 反向的第一和第二电极在电阻可变硫属化物材料上可操作地接收。 至少一个电极具有延伸到电阻可变硫族化物材料中的导电突起。

公开(公告)号：US07157778B2

公开(公告)日：2007-01-02

申请号：US11018848

申请日：2004-12-20

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L21/823462 ,  H01L21/3145 ,  H01L21/31612

摘要： The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate. After the nitrogen-comprising layer is formed, a second oxide region is grown from the second region of the substrate. A first transistor gate is formed over the first oxide region, and a second transistor gate is formed over the second oxide region.

摘要翻译： 本发明包括在半导体衬底上形成氧化物区域的方法。 在至少一些基底上形成含氮层。 在形成含氮层之后，从衬底中的至少一些生长氧化物区域。 含氮层的氮分散在氧化物区域内。 本发明还包括形成与半导体衬底相关联的一对晶体管的方法。 提供基板。 限定衬底的第一区域，并且另外定义衬底的第二区域。 形成第一氧化物区域，其覆盖衬底的第一区域中的至少一些，并且不覆盖衬底的任何第二区域。 跨越第一氧化物区域中的至少一些并穿过衬底的至少一些第二区域形成含氮层。 在形成含氮层之后，从衬底的第二区域生长第二氧化物区域。 在第一氧化物区域上形成第一晶体管栅极，在第二氧化物区域上形成第二晶体管栅极。

公开(公告)号：US07151273B2

公开(公告)日：2006-12-19

申请号：US10120521

申请日：2002-04-12

申请人： Kristy A. Campbell ,  John T. Moore

发明人： Kristy A. Campbell ,  John T. Moore

IPC分类号： H01L29/04

CPC分类号： G11C13/0011 ,  G11C2213/51 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/1625

摘要： The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100−x composition.

摘要翻译： 本发明涉及用于提供具有改进的数据保持和切换特性的电阻可变存储元件的方法和装置。 根据本发明的实施例，提供了一种电阻可变存储元件，其在玻璃层之间具有至少一个硒化银层，其中至少一个玻璃层是硫族化物玻璃，优选具有Ge x 100＆lt; 100＆lt; 100＆gt;组合物。