公开(公告)号：US20050090056A1

公开(公告)日：2005-04-28

申请号：US10692612

申请日：2003-10-24

申请人： Heon Lee

发明人： Heon Lee

IPC分类号： H01L21/336 ,  H01L27/22 ,  H01L31/113 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L43/12

摘要： A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact with a portion of the magnetic tunnel junction stack. The spacer electrically insulates a portion of the magnetic tunnel junction stack from an electrically conductive material used for a via that is in contact with the magnetic tunnel junction stack and a top conductor. The spacer can also prevent an electrical short between a bottom conductor and the top conductor. The spacer can prevent electrical shorts when the magnetic tunnel junction stack and a self-aligned via are not aligned with each other.

摘要翻译： 公开了制造磁性隧道结装置的方法。 磁性隧道结装置包括磁性隧道结叠层和与磁性隧道结叠层的一部分接触的非导电间隔物。 间隔件将磁性隧道结堆叠的一部分与用于与磁性隧道结叠层和顶部导体接触的通路的导电材料电绝缘。 隔离器还可以防止底部导体和顶部导体之间的电短路。 当磁性隧道结堆叠和自对准通孔彼此不对齐时，间隔件可以防止电气短路。

公开(公告)号：US20050018884A1

公开(公告)日：2005-01-27

申请号：US10898487

申请日：2004-07-22

申请人： Heon Lee ,  Don Lee

发明人： Heon Lee ,  Don Lee

IPC分类号： G01B7/28 ,  A61B5/117 ,  G06K9/00 ,  G06T1/00

CPC分类号： G06K9/00053

摘要： A fingerprint sensor of the present invention includes a substrate; a plurality of electrode patterns formed on the substrate for detecting an impedance signal in response to the contact of a fingerprint; and an insulating layer formed on the substrate including the electrode patterns.

摘要翻译： 本发明的指纹传感器包括：基板; 形成在所述基板上的多个电极图案，用于响应于指纹的接触来检测阻抗信号; 以及形成在包括电极图案的基板上的绝缘层。

公开(公告)号：US20050018526A1

公开(公告)日：2005-01-27

申请号：US10772141

申请日：2004-02-03

申请人： Heon Lee

发明人： Heon Lee

IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C8/02

CPC分类号： H01L45/06 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/16

摘要： The present invention is to provide a phase change memory device having a new structure which can be easily manufactured by mass-production with a high yield rate, therefore, reducing the cost of process and providing reliable device characteristics, and a manufacturing method thereof. The present invention provides a phase-change memory device comprising: a lower dielectric layer; a lower electrode, at least a part of the lateral surface of the lower electrode being surrounded by the lower dielectric layer; a thin dielectric layer including a pore having smaller area than the top surface of the lower electrode, aligned to the top surface of the lower electrode and extending to the top surface of the lower electrode; and a phase-change resistor filling the pore and formed on the thin dielectric layer. In the proposed structure of the present invention, the pores or local damaged spots can provide a micro path of current and localize the phase-changing volume in the phase-change resistor. Thus, the phase-change memory device can be operated with very low power.

摘要翻译： 本发明提供一种具有新结构的相变存储器件及其制造方法，该相变存储器件可以容易地通过批量生产以高产率制造，从而降低工艺成本并提供可靠的器件特性。 本发明提供了一种相变存储器件，包括：下介电层; 下电极，下电极的侧表面的至少一部分被下电介质层包围; 包括具有比下电极的顶表面小的面积的孔的薄介电层，与下电极的顶表面对准并延伸到下电极的顶表面; 以及填充所述孔并形成在所述薄介电层上的相变电阻器。 在本发明的所提出的结构中，孔或局部损坏的斑点可以提供微通路并使相变电阻器中的相变体积定位。 因此，可以以非常低的功率来操作相变存储器件。

公开(公告)号：US06839271B1

公开(公告)日：2005-01-04

申请号：US10685618

申请日：2003-10-15

申请人： Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee

发明人： Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee

IPC分类号： H01L27/105 ,  G11C11/00 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L43/08

CPC分类号： G11C11/16

摘要： A magnetic memory device which comprises a magnetic memory cell that includes a magnetic material switchable between two resistive states on the application of a magnetic field. The device also comprises a wire that is connected to the magnetic memory cell and has a conductive connecting link and a conductive word or bit line which are electrically connected to each other. The connecting link is disposed between the word or bit line and the magnetic memory cell and has a thermal resistance that is larger than that of the word or bit line so as to provide a barrier for heat conduction from the magnetic memory cell to the word or bit line.

公开(公告)号：US06665205B2

公开(公告)日：2003-12-16

申请号：US10079311

申请日：2002-02-20

申请人： Heon Lee ,  Fred Perner

发明人： Heon Lee ,  Fred Perner

IPC分类号： G11C508

CPC分类号： G11C11/16 ,  G11C11/15

摘要： The invention includes an apparatus and a method that provides a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell. The first memory cell and the second memory cell can be MRAM devices. A logical state of the MRAM devices can be determined by an orientation of magnetization of the MRAM devices. The orientation of magnetization of the first memory cell can be determined by current conducted by the first bit line and the global word line. The orientation of magnetization of the second memory cell can be determined by current conducted by the second bit line and the global word line. A logical state of the first memory cell can be sensed by the first bit line and the first sense line. The logical state of the first memory cell can be determined by a sensing a resistance between the first bit line and the first sense line. A logical state of the second memory cell can be sensed by the second bit line and the second sense line. The logical state of the second memory cell can be determined by a sensing a resistance between the second bit line and the second sense line.

公开(公告)号：US06621096B2

公开(公告)日：2003-09-16

申请号：US09860524

申请日：2001-05-21

申请人： Heon Lee ,  Chung-Ching Yang ,  Peter Hartwell

发明人： Heon Lee ,  Chung-Ching Yang ,  Peter Hartwell

IPC分类号： H01L2906

CPC分类号： B82Y10/00 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/149 ,  H01L21/764 ,  Y10S977/723

摘要： A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.

公开(公告)号：US06414347B1

公开(公告)日：2002-07-02

申请号：US09790011

申请日：2001-02-09

申请人： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

发明人： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

IPC分类号： H01L2972

CPC分类号： H01L27/10864 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10841 ,  H01L29/66666 ,  H01L29/7827

摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

摘要翻译： 一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层 基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。

公开(公告)号：US06362033B1

公开(公告)日：2002-03-26

申请号：US09460318

申请日：1999-12-14

申请人： Heon Lee ,  Young-Jin Park

发明人： Heon Lee ,  Young-Jin Park

IPC分类号： H01L21338

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32137

摘要： A method for forming a transistor is formed where a gate electrode of the transistor is formed over a substrate defining a gate channel portion of the substrate. A mask is also formed over the substrate, a portion of the mask extending over a first portion of the substrate adjacent to the gate channel portion of the substrate. The mask defines a second portion of the substrate adjacent to the first portion of the substrate. An ion beam is directed toward the substrate to form a drain or a source region of said transistor adjacent to the gate channel portion of the substrate, the source or drain region including the first and second portions of the substrate. The ion beam implants the second portion of the substrate with a first implantation characteristic. The ion beam passes through the extended portion of the mask to reach the first portion to implant the first portion with a second implantation characteristic, such second implantation characteristic being different from the first implantation characteristic.

摘要翻译： 形成晶体管的方法形成在晶体管的栅电极形成在限定衬底的栅极沟道部分的衬底上。 掩模也形成在衬底上，掩模的一部分在与衬底的栅极沟道部分相邻的衬底的第一部分上延伸。 掩模限定与基板的第一部分相邻的基板的第二部分。 离子束指向衬底以形成与衬底的栅极沟道部分相邻的所述晶体管的漏极或源极区域，源极或漏极区域包括衬底的第一和第二部分。 离子束以第一注入特性注入衬底的第二部分。 离子束通过掩模的延伸部分到达第一部分以将第一部分注入第二注入特性，这种第二注入特性与第一注入特性不同。

公开(公告)号：US20120121983A1

公开(公告)日：2012-05-17

申请号：US13084236

申请日：2011-04-11

申请人： Woo-Young Yoon ,  Heon Lee ,  Dae-Gun Jin

发明人： Woo-Young Yoon ,  Heon Lee ,  Dae-Gun Jin

IPC分类号： H01M4/58 ,  B05D5/12 ,  G03F7/20 ,  H01M4/1395

CPC分类号： H01M4/661 ,  H01M4/0404

摘要： The present invention relates to a lithium deposited anode for a lithium secondary battery and a method for preparing the same, and more particularly, to an anode suitable for a lithium secondary battery which limits dendrite growth only inside the concave portion of the silicon substrate during a battery is charged/discharged by depositing lithium as an active material only on the deeply caved concave portion of an anode current collector of which a micro-size patterned silicon substrate has conductivity provided by a metal, and its manufacturing method.

摘要翻译： 锂二次电池的锂沉积阳极及其制备方法技术领域本发明涉及一种用于锂二次电池的锂沉积阳极及其制备方法，更具体地说，涉及一种适于锂二次电池的阳极，该锂二次电池仅在硅衬底的凹部内限制枝晶生长， 电池通过仅将锂作为活性材料沉积在阳极集电体的深度凹陷部分上，其中微型尺寸图案化的硅衬底具有由金属提供的导电性及其制造方法。

公开(公告)号：US07259062B2

公开(公告)日：2007-08-21

申请号：US10692612

申请日：2003-10-24

申请人： Heon Lee

发明人： Heon Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/222 ,  H01L43/12

摘要： A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact with a portion of the magnetic tunnel junction stack. The spacer electrically insulates a portion of the magnetic tunnel junction stack from an electrically conductive material used for a via that is in contact with the magnetic tunnel junction stack and a top conductor. The spacer can also prevent an electrical short between a bottom conductor and the top conductor. The spacer can prevent electrical shorts when the magnetic tunnel junction stack and a self-aligned via are not aligned with each other.

摘要翻译： 公开了制造磁性隧道结装置的方法。 磁性隧道结装置包括磁性隧道结叠层和与磁性隧道结叠层的一部分接触的非导电间隔物。 间隔件将磁性隧道结堆叠的一部分与用于与磁性隧道结叠层和顶部导体接触的通路的导电材料电绝缘。 隔离器还可以防止底部导体和顶部导体之间的电短路。 当磁性隧道结堆叠和自对准通孔彼此不对齐时，间隔件可以防止电气短路。