公开(公告)号：US20240250181A1

公开(公告)日：2024-07-25

申请号：US18595629

申请日：2024-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Keisuke MURAYAMA

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/7831

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

公开(公告)号：US20220293798A1

公开(公告)日：2022-09-15

申请号：US17826265

申请日：2022-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Yutaka OKAZAKI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04 ,  H01L29/49

Abstract: A transistor in which a short-channel effect is not substantially caused and which has switching characteristics even in the case where the channel length is short is provided. Further, a highly integrated semiconductor device including the transistor is provided. A short-channel effect which is caused in a transistor including silicon is not substantially caused in the transistor including an oxide semiconductor film. The channel length of the transistor including the oxide semiconductor film is greater than or equal to 5 nm and less than 60 nm, and the channel width thereof is greater than or equal to 5 nm and less than 200 nm. At this time, the channel width is made 0.5 to 10 times as large as the channel length.

公开(公告)号：US20210090961A1

公开(公告)日：2021-03-25

申请号：US16629602

申请日：2018-07-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuki TANEMURA ,  Etsuko KAMATA ,  Hiromi SAWAI ,  Daisuke MATSUBAYASHI

IPC: H01L21/84 ,  H01L21/822 ,  H01L27/12

Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.

公开(公告)号：US20190288093A1

公开(公告)日：2019-09-19

申请号：US16429176

申请日：2019-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Yukinori SHIMA ,  Hajime TOKUNAGA ,  Toshinari SASAKI ,  Keisuke MURAYAMA ,  Daisuke MATSUBAYASHI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/51 ,  H01L21/02 ,  H01L27/12

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

公开(公告)号：US20180294363A1

公开(公告)日：2018-10-11

申请号：US16003145

申请日：2018-06-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Yukinori SHIMA ,  Hajime TOKUNAGA ,  Toshinari SASAKI ,  Keisuke MURAYAMA ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02 ,  H01L29/24

Abstract: In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

公开(公告)号：US20170040457A1

公开(公告)日：2017-02-09

申请号：US15224958

申请日：2016-08-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Daisuke MATSUBAYASHI ,  Yuichi SATO

IPC: H01L29/786 ,  H01L29/45 ,  H01L21/441 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.

Abstract translation: 提供其中寄生电容减小的半导体器件。 第一绝缘层沉积在衬底上。 在第一绝缘层上沉积第一氧化物绝缘层和氧化物半导体层。 第二氧化物绝缘层沉积在氧化物半导体层和第一绝缘层上。 在第二氧化物绝缘层上沉积第二绝缘层和第一导电层。 通过蚀刻形成栅极电极层，栅极绝缘层和第三氧化物绝缘层。 形成包括与栅电极层的侧面接触的区域的侧壁绝缘层。 在栅电极层，侧壁绝缘层，氧化物半导体层和第一绝缘层上沉积第二导电层。 在第二导电层上沉积第三导电层。 通过进行热处理，在氧化物半导体层中形成低电阻区域。 包含在第二导电层中的元素通过进行热处理从第二导电层移动到氧化物半导体层侧。 包含在氧化物半导体层中的元素通过进行热处理从氧化物半导体层移动到第三导电层侧。

公开(公告)号：US20170033204A1

公开(公告)日：2017-02-02

申请号：US15290359

申请日：2016-10-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI

IPC: H01L29/66 ,  H01L21/441 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/441 ,  H01L29/78648 ,  H01L29/7869

Abstract: A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.

Abstract translation: 第一源电极形成为与半导体层接触; 形成与半导体层接触的第一漏电极; 形成第二源电极，其延伸超过第一源电极的与半导体层接触的端部; 形成第二漏电极，其延伸超过所述第一漏电极的与所述半导体层接触的端部; 第一侧壁形成为与第二源电极和半导体层的侧表面接触; 第二侧壁形成为与第二漏电极和半导体层的侧表面接触; 并且形成栅电极以与第一侧壁，第二侧壁和半导体层重叠，其间设置有栅极绝缘层。

公开(公告)号：US20160190347A1

公开(公告)日：2016-06-30

申请号：US15062268

申请日：2016-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Kazuya HANAOKA ,  Yoshiyuki KOBAYASHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

公开(公告)号：US20160149045A1

公开(公告)日：2016-05-26

申请号：US14941930

申请日：2015-11-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Daisuke MATSUBAYASHI ,  Kazuki TANEMURA

IPC: H01L29/786 ,  H01L29/788

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/14612 ,  H01L29/1083 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/788 ,  H01L29/7881

Abstract: A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The electron trap layer overlaps with the channel formation region with the second insulator interposed therebetween. The first conductor overlaps with the channel formation region with the first insulator interposed therebetween. The second conductor overlaps with the electron trap layer with the third insulator interposed therebetween. The second conductor does not overlap with the channel formation region.

Abstract translation: 半导体器件包括第一导体，第二导​​体，第一绝缘体，第二绝缘体，第三绝缘体，半导体和电子陷阱层。 半导体包括沟道形成区域。 电子捕获层与通道形成区域重叠，其间插入第二绝缘体。 第一导体与沟道形成区重叠，其间插入第一绝缘体。 第二导体与电子陷阱层重叠，其间插入第三绝缘体。 第二导体不与沟道形成区重叠。

公开(公告)号：US20160005871A1

公开(公告)日：2016-01-07

申请号：US14753426

申请日：2015-06-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinpei MATSUDA ,  Toshihiko TAKEUCHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: A transistor with a small subthreshold swing value is provided. A transistor with a low density of shallow interface states at an interface between a semiconductor and a gate insulator is provided. A transistor with favorable electrical characteristics is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. The semiconductor includes a region in which the semiconductor and the conductor overlap each other with the insulator positioned therebetween, and the density of shallow interface states at an interface between the semiconductor and the insulator in the region is lower than or equal to 1×1013 cm−2.

Abstract translation: 提供了具有小的亚阈值摆动值的晶体管。 提供了在半导体和栅极绝缘体之间的界面处具有低接合态的低密度晶体管。 提供具有良好电特性的晶体管。 半导体器件包括绝缘体，半导体和导体。 半导体包括半导体和导体彼此重叠的区域，绝缘体位于它们之间，并且该区域中的半导体与绝缘体之间的界面处的浅界面状态的密度低于或等于1×1013cm -2。