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265 条记录 (耗时 0.034 秒)

    Doped copper interconnects using laser thermal annealing
    31.
    发明授权
    Doped copper interconnects using laser thermal annealing 失效
    使用激光热退火的掺杂铜互连

    公开(公告)号：US06731006B1

    公开(公告)日：2004-05-04

    申请号：US10323941

    申请日：2002-12-20

    申请人： Arvind Halliyal ,  Minh Van Ngo

    发明人： Arvind Halliyal ,  Minh Van Ngo

    IPC分类号： H01L2348

    CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method of making the same includes a first metallization level, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer and the first etch stop layer. The first etch stop layer is disposed over the first metallization level. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. Dopants are introduced into the metal and are activated by laser thermal annealing. A concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature, and a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature.

    摘要翻译： 半导体器件及其制造方法包括第一金属化层，第一蚀刻停止层，电介质层和延伸穿过介电层和第一蚀刻停止层的开口。 第一蚀刻停止层设置在第一金属化层上。 开口内的金属形成第二金属特征，金属可以包括铜或铜合金。 将掺杂剂引入金属中并通过激光热退火来激活。 在第二金属特征附近的第二金属特征的下部中的金属内的掺杂剂的浓度大于第二金属特征的中心部分中的掺杂剂的浓度，并且金属中掺杂剂的浓度在 第二金属特征的上部大于第二金属特征的中心部分中的掺杂剂的浓度。

    Method of forming reliable Cu interconnects
    32.
    发明授权
    Method of forming reliable Cu interconnects 失效
    形成可靠的Cu互连的方法

    公开(公告)号：US06727176B2

    公开(公告)日：2004-04-27

    申请号：US09986267

    申请日：2001-11-08

    申请人： Minh Van Ngo ,  Arvind Halliyal ,  Eric Paton

    发明人： Minh Van Ngo ,  Arvind Halliyal ,  Eric Paton

    IPC分类号： H01L2144

    CPC分类号： H01L21/76882

    摘要： Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.

    摘要翻译： 通过用Cu填充电介质层中的开口，然后在NH 3中激光热退火以形成可靠的Cu互连，以减少氧化铜和回流沉积的Cu，从而消除空隙并降低接触电阻。 实施例包括使用约200至约2,000sccn的NH 3流速的激光热退火。

    Method of forming reliable capped copper interconnects
    33.
    发明授权
    Method of forming reliable capped copper interconnects 有权
    形成可靠封盖铜互连的方法

    公开(公告)号：US06660634B1

    公开(公告)日：2003-12-09

    申请号：US10291612

    申请日：2002-11-12

    申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

    发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

    IPC分类号： H01L2144

    CPC分类号： H01L21/76862 ,  H01L21/76801 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/902 ,  Y10S438/906 ,  H01L2924/00

    摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

    摘要翻译： 扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附通过处理Cu或Cu合金互连构件的暴露表面而显着增强：（a）在等离子体条件下用氨和硅烷或二氯硅烷形成铜 硅化物层; 或（b）与氨等离子体接触，然后与硅烷或二氯硅烷反应，在其上形成硅化铜层。 然后将扩散阻挡层沉积在硅化铜层上。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，然后处理Cu / Cu合金互连的暴露表面以在其上形成硅化铜层，并沉积氮化硅 扩散阻挡层在硅化铜层上。

    Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation
    34.
    发明授权
    Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation 失效
    在具有从气体前体沉积的硅层的半导体晶片中形成超浅结的方法，以减少在水化过程中的硅消耗

    公开(公告)号：US06660621B1

    公开(公告)日：2003-12-09

    申请号：US10163461

    申请日：2002-06-07

    申请人： Paul R. Besser ,  Minh Van Ngo

    发明人： Paul R. Besser ,  Minh Van Ngo

    IPC分类号： H01L213205

    CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/665

    摘要： A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.

    摘要翻译： 在半导体晶片中形成超浅结的方法形成栅极和源极/漏极结，其在栅极和源极/漏极结上的第一金属硅化物区具有上表面。 这些第一金属硅化物区域具有较高的电阻率。 通过等离子体增强化学气相沉积（PECVD）将非晶硅沉积在第一金属硅化物区域上。 PECVD工艺可以是较低压力的沉积工艺，在多个工位上执行以在多层中形成非晶硅层。 这就形成了跨越晶片的更均匀的非晶硅层和不同的图案化密度，从而提高了器件性能和特性。 然后通过第一金属硅化物区域和通过PECVD工艺沉积的非晶硅的扩散反应，进行退火以形成较低电阻率的第二金属硅化物区域。

    Method of manufacturing a semiconductor device with reliable contacts/vias
    36.
    发明授权
    Method of manufacturing a semiconductor device with reliable contacts/vias 有权
    制造具有可靠接触/通孔的半导体器件的方法

    公开(公告)号：US06576548B1

    公开(公告)日：2003-06-10

    申请号：US10079861

    申请日：2002-02-22

    申请人： Amy Tu ,  Minh Van Ngo ,  Austin Frenkel ,  Robert J. Chiu ,  Jeff Erhardt

    发明人： Amy Tu ,  Minh Van Ngo ,  Austin Frenkel ,  Robert J. Chiu ,  Jeff Erhardt

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/31105 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76877

    摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.

    摘要翻译： 通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。 所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。 实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层， 在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨 约1,900至约2,300埃/分钟以填充开口。

    Silicon oxide liner for reduced nickel silicide bridging
    37.
    发明授权
    Silicon oxide liner for reduced nickel silicide bridging 有权
    用于还原硅化镍桥接的氧化硅衬垫

    公开(公告)号：US06548403B1

    公开(公告)日：2003-04-15

    申请号：US09679871

    申请日：2000-10-05

    申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

    发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L29/6659

    摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by forming a relatively thick silicon oxide liner on the side surfaces of the gate electrode and adjacent surface of the semiconductor substrate before forming the silicon nitride sidewall spacers thereon. Embodiments include forming a silicon dioxide liner at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers thereon.

    摘要翻译： 在形成氮化硅侧壁之前，通过在栅电极的侧表面和半导体衬底的相邻表面上形成相对较厚的氧化硅衬垫来防止在栅电极上的硅化镍层与氮化硅侧壁间隔物之间​​的源极/漏极区之间的桥接 垫片。 在形成氮化硅侧壁间隔物之前，实施例包括在大约至大约600埃的厚度形成二氧化硅衬垫。

    Semiconductor device comprising copper interconnects with reduced in-line copper diffusion
    39.
    发明授权
    Semiconductor device comprising copper interconnects with reduced in-line copper diffusion 有权
    包括具有减少的在线铜扩散的铜互连的半导体器件

    公开(公告)号：US06472755B1

    公开(公告)日：2002-10-29

    申请号：US09688928

    申请日：2000-10-17

    申请人： Minh Van Ngo ,  Takeshi Nogami

    发明人： Minh Van Ngo ,  Takeshi Nogami

    IPC分类号： H01L2348

    CPC分类号： H01L23/53238 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.

    摘要翻译： 通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅，然后沉积氧化硅层，从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件（例如线）之间的Cu扩散 盖层 实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP，以实现平面化，使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面 用高强度氨等离子体离子轰击具有氮原子的暴露的线间氧化硅，从而将上部转化为氮氧化硅，同时除去或显着还原线上的表面氧化物。 然后沉积氮化硅覆盖层。