公开(公告)号：US20060276027A1

公开(公告)日：2006-12-07

申请号：US11144742

申请日：2005-06-06

申请人： Yung-Cheng Lu ,  Ming-Hsing Tsai

发明人： Yung-Cheng Lu ,  Ming-Hsing Tsai

IPC分类号： H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one stress-harmonizing layer to electrically connect the conductive member.

公开(公告)号：US06793797B2

公开(公告)日：2004-09-21

申请号：US10106733

申请日：2002-03-26

申请人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Winston Shue ,  Mong-Song Liang

发明人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Winston Shue ,  Mong-Song Liang

IPC分类号： C25D518

CPC分类号： H01L21/2885 ,  B23H5/08 ,  C25D5/18 ,  C25D7/123 ,  H01L21/32125 ,  H01L21/76877

摘要： A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.

摘要翻译： 一种用于交替电沉积和电机械抛光以选择性地用金属填充半导体特征的方法，包括：a）提供以间隔开的关系设置的阳极组件和半导体晶片，所述阳极组件和半导体晶片在半导体晶片之间包括电解质，所述电解质包括包括各向异性蚀刻特征 安排电沉积过程; b）在阳极组件和半导体晶片之间施加电位以在第一电流密度下引起电解质流动，以将金属填充部分电沉积到工艺表面上; c）逆转电位以在第二电流密度下反转电解质流动，以在电抛光过程中电镀处理表面; 以及d）依次重复步骤b和c以电沉积至少第二金属填充部分以基本上填充各向异性蚀刻的特征。

公开(公告)号：US06706166B2

公开(公告)日：2004-03-16

申请号：US10139975

申请日：2002-05-06

申请人： Shih-Wei Chou ,  Ming-Hsing Tsai

发明人： Shih-Wei Chou ,  Ming-Hsing Tsai

IPC分类号： C25D500

CPC分类号： H01L21/76877 ,  C25D5/18 ,  C25D7/12 ,  C25D17/001 ,  C25D17/10 ,  H01L21/2885

摘要： A method for improving an electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process including providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath including a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly including the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.

摘要翻译： 一种在电沉积和电解抛光过程中改善电沉积金属膜均匀性和防止金属沉积和从电极剥离的方法，包括提供第一阳极电极组件和半导体晶片电镀表面，该表面设置在包括电镀金属的电解液中 沉积到半导体晶片电镀表面上; 提供至少一个额外的阳极电极组件，其包括设置在所述第一阳极电极组件周围的电镀金属，用于在电抛光工艺期间选择性地施加阴极电位; 并且在相对于半导体晶片电镀表面的电沉积工艺和电解抛光工艺之间周期性地交替，使得电镀金属优先地镀在至少一个附加电极组件上。

公开(公告)号：US06660577B2

公开(公告)日：2003-12-09

申请号：US10083277

申请日：2002-02-23

申请人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

发明人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

IPC分类号： H01L218249

CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4966

摘要： A method for fabricating metal gates in deep sub-micron CMOS devices. The method blanket deposits a transition metal nitride layer on top of a gate dielectric layer for forming gate electrodes for both a PMOS and an NMOS device. After a cap layer is deposited on top of the gate electrode for PMOS, a rapid thermal annealing process is carried out to drive out nitrogen from the transition metal nitride on top of the NMOS. Gate electrodes having different work functions on top of the PMOS and NMOS are thus achieved simultaneously by the same fabrication process.

摘要翻译： 一种在深亚微米CMOS器件中制造金属栅极的方法。 该方法覆盖在栅介电层的顶部沉积过渡金属氮化物层，以形成用于PMOS和NMOS器件的栅电极。 在用于PMOS的栅电极的顶部上沉积覆盖层之后，进行快速热退火处理以从NMOS顶部的过渡金属氮化物驱出氮。 因此，通过相同的制造工艺同时实现在PMOS和NMOS之上具有不同功函数的栅电极。

公开(公告)号：US06300250B1

公开(公告)日：2001-10-09

申请号：US09369260

申请日：1999-08-09

申请人： Ming-Hsing Tsai

发明人： Ming-Hsing Tsai

IPC分类号： H01L21311

CPC分类号： H01L24/12 ,  H01L21/2885 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10S438/959 ,  H01L2924/00

摘要： A new method is provided to create metal bumps on a surface, metal contact pads have been provided in this surface. A layer of dielectric is deposited over a surface; an opening is created in the layer of dielectric that aligns with the contact pad. A barrier layer is deposited over the layer of dielectric including the inside of the opening; a seed layer is deposited over the barrier layer. The seed layer is selectively removed from above the layer of dielectric leaving the seed layer intact and deposited over the inside surfaces of the opening, the barrier layer is left intact over the layer of dielectric and inside the opening. Using Electrical Chemical Deposition (ECD) technology, the metal bump is now selectively grown thereby eliminating previously experienced disadvantages when creating metal bumps of decreased pitch and mask alignments and resolution.

摘要翻译： 提供了一种在表面上形成金属凸块的新方法，在该表面上提供了金属接触垫。 电介质层沉积在表面上; 在与接触垫对准的电介质层中产生开口。 阻挡层沉积在包括开口内部的电介质层上; 种子层沉积在阻挡层上。 种子层从介质层上方选择性地去除，离开种子层完整并沉积在开口的内表面上，阻挡层完整地保留在电介质层和开口内部。 使用电化学沉积（ECD）技术，金属凸块现在被选择性地生长，从而消除了以前经历的缺点，当产生具有降低的间距和掩模对准和分辨率的金属凸块时。

公开(公告)号：US5668054A

公开(公告)日：1997-09-16

申请号：US584749

申请日：1996-01-11

申请人： Shi-Chung Sun ,  Hien-Tien Chiu ,  Ming-Hsing Tsai

发明人： Shi-Chung Sun ,  Hien-Tien Chiu ,  Ming-Hsing Tsai

IPC分类号： C23C16/34 ,  H01L21/285 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76843 ,  C23C16/34 ,  H01L21/28556

摘要： A process for fabricating a tantalum nitride diffusion barrier for the advanced copper metallization of semiconductor devices is disclosed. The process comprises the steps of first preparing a semiconductor device fabricated over the surface of a silicon substrate having a component with a fabricated contact opening. Before the formation of the copper contact by deposition, the process performs a tantalum nitride low-pressure chemical-vapor-deposition procedure that deposits a layer of tantalum nitride thin film over the surface of the device substrate. After the copper deposition, a photoresist layer is subsequently fabricated for patterning the deposited copper contact and tantalum nitride layers, whereby the deposited thin film of tantalum nitride is patterned to form the thin film as the metallization diffusion barrier for the semiconductor device. The tantalum nitride low-pressure chemical-vapor-deposition procedure includes depositing a layer of tantalum nitride utilizing a metal-organic precursor terbutylimido-tris-diethylamido tantalum (TBTDET) in a cold-wall low pressure reactor with a base pressure of about 10.sup.-5 torr. The source of the metal-organic precursor is vaporized at a temperature of about 40.degree. to 50.degree. C. The typical deposition pressure is about 20 mtorr. Tantalum nitride layer of low carbon content and low resistivity may thus be formed in the disclosed chemical-vapor-deposition procedure having effective capability against copper diffusion.

摘要翻译： 公开了一种用于制造用于半导体器件的先进铜金属化的氮化钽扩散阻挡层的工艺。 该方法包括以下步骤：首先制备在具有制造的接触开口的部件的硅衬底的表面上制造的半导体器件。 在通过沉积形成铜接触之前，该工艺执行在器件衬底的表面上沉积氮化钽薄层的氮化钽低压化学气相沉积工艺。 在铜沉积之后，随后制造光致抗蚀剂层以图案化沉积的铜接触和氮化钽层，由此沉积的氮化钽薄膜被图案化以形成作为半导体器件的金属化扩散阻挡层的薄膜。 氮化钽低压化学气相沉积方法包括使用金属有机前体叔丁基亚氨基 - 三 - 二乙基氨基钽（TBTDET）在基本压力为约10 -6的冷壁低压反应器中沉积氮化钽层， 5托 金属有机前体的来源在约40℃至50℃的温度下蒸发。典型的沉积压力为约20毫托。 因此，可以在具有对铜扩散的有效能力的公开的化学气相沉积方法中形成低碳含量和低电阻率的氮化钽层。

公开(公告)号：US07638859B2

公开(公告)日：2009-12-29

申请号：US11144742

申请日：2005-06-06

申请人： Yung-Cheng Lu ,  Ming-Hsing Tsai

发明人： Yung-Cheng Lu ,  Ming-Hsing Tsai

IPC分类号： H01L23/58 ,  H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one stress-harmonizing layer to electrically connect the conductive member.

摘要翻译： 具有协调应力的互连和制造它的方法。 互连件包括具有导电部件的基板。 插入其中的至少一个应力协调层的复合低k电介质层覆盖在基板上。 复合低k电介质层中的导电特征通过至少一个应力协调层以电连接导电构件。

公开(公告)号：US20070052096A1

公开(公告)日：2007-03-08

申请号：US11210226

申请日：2005-08-23

申请人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

IPC分类号： H01L21/4763

CPC分类号： H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

摘要翻译： 提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。 提供了一种半导体器件，包括衬底。 其中具有至少一个导电特征的电介质层覆盖在衬底上。 绝缘覆盖层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。

公开(公告)号：US20060243596A1

公开(公告)日：2006-11-02

申请号：US11119183

申请日：2005-04-28

申请人： Ming-Wei Lin ,  Ming-Hsing Tsai

发明人： Ming-Wei Lin ,  Ming-Hsing Tsai

IPC分类号： C25D7/12 ,  C25D17/06

CPC分类号： C25D17/06 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  H01L21/2885

摘要： An electrochemical plating apparatus and method for facilitating uniform current distribution across a wafer during loading into an ECP (electrochemical plating) apparatus is disclosed. The apparatus includes a bath container for containing a bath solution, an anode provided in the bath container, a cathode ring for supporting a wafer in the bath container and a current source electrically connected to the anode and the cathode ring. According to the method, a voltage potential is applied to the cathode ring as it is immersed into the solution and prior to immersion of the wafer in the solution, thereby facilitating a substantially uniform plating current across the wafer upon immersion of the wafer.

公开(公告)号：US20060189127A1

公开(公告)日：2006-08-24

申请号：US11410229

申请日：2006-04-24

申请人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

发明人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/7684 ,  H01L21/76877 ,  H05K3/423

摘要： Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.

摘要翻译： 衬底中的窄沟槽倾向于比宽沟槽更快地填充。这导致一旦所有沟槽都被填充，就会形成非平面表面。 本发明通过两步进行电沉积来解决这个问题。 在第一步骤期间使用的电镀槽在针对第二步骤期间使用的电镀槽进行优化以优化用于填充窄沟槽的情况下进行优化，以优化填充宽的沟槽。 最终的结果是具有平坦表面的最终层，其中所有的沟槽被正确填充。