公开(公告)号：US20060054508A1

公开(公告)日：2006-03-16

申请号：US10943744

申请日：2004-09-16

申请人： Ming-Wei Lin ,  Ming-Hsing Tsai

发明人： Ming-Wei Lin ,  Ming-Hsing Tsai

IPC分类号： C25D3/48 ,  C25D3/38 ,  C25D5/48

CPC分类号： H01L21/2885 ,  C25D3/02 ,  C25D3/38 ,  H01L21/7684

摘要： A new and improved method for electroplating a metal onto a substrate in such a manner as to render the metal essentially corrosion-resistant during subsequent substrate processing such as chemical mechanical polishing. The process involves incorporating nitrogen into the metal as the metal is electroplated onto the substrate. The process includes preparing the electroplating bath, placing a leveler chemical containing nitrogen in the prepared bath, circulating the leveler chemical throughout the bath and then electroplating the metal on the substrate. In a preferred embodiment, alkyl polyamide, alkyl amine, alkyl amine oxide or thiourea with molecular weight ranging from 100˜1,000,000 is used as the leveler chemical.

摘要翻译： 一种新的和改进的方法，用于将金属电镀到基底上，使得金属在随后的基底处理（例如化学机械抛光）中基本上具有耐腐蚀性。 该方法包括在将金属电镀到基底上时将氮掺入金属中。 该方法包括制备电镀浴，将准备好的浴中含有氮的矫正剂化学品放置在整个浴中，使整平剂化学品循环，然后将金属电镀在基底上。 在优选的实施方案中，使用分子量为100〜1,000,000的烷基聚酰胺，烷基胺，烷基氧化胺或硫脲作为矫光剂。

公开(公告)号：US20060243596A1

公开(公告)日：2006-11-02

申请号：US11119183

申请日：2005-04-28

申请人： Ming-Wei Lin ,  Ming-Hsing Tsai

发明人： Ming-Wei Lin ,  Ming-Hsing Tsai

IPC分类号： C25D7/12 ,  C25D17/06

CPC分类号： C25D17/06 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  H01L21/2885

摘要： An electrochemical plating apparatus and method for facilitating uniform current distribution across a wafer during loading into an ECP (electrochemical plating) apparatus is disclosed. The apparatus includes a bath container for containing a bath solution, an anode provided in the bath container, a cathode ring for supporting a wafer in the bath container and a current source electrically connected to the anode and the cathode ring. According to the method, a voltage potential is applied to the cathode ring as it is immersed into the solution and prior to immersion of the wafer in the solution, thereby facilitating a substantially uniform plating current across the wafer upon immersion of the wafer.

公开(公告)号：US20060189127A1

公开(公告)日：2006-08-24

申请号：US11410229

申请日：2006-04-24

申请人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

发明人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/7684 ,  H01L21/76877 ,  H05K3/423

摘要： Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.

摘要翻译： 衬底中的窄沟槽倾向于比宽沟槽更快地填充。这导致一旦所有沟槽都被填充，就会形成非平面表面。 本发明通过两步进行电沉积来解决这个问题。 在第一步骤期间使用的电镀槽在针对第二步骤期间使用的电镀槽进行优化以优化用于填充窄沟槽的情况下进行优化，以优化填充宽的沟槽。 最终的结果是具有平坦表面的最终层，其中所有的沟槽被正确填充。

公开(公告)号：US07064068B2

公开(公告)日：2006-06-20

申请号：US10763306

申请日：2004-01-23

申请人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

发明人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/7684 ,  H01L21/76877 ,  H05K3/423

摘要： Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.

摘要翻译： 衬底中的窄沟槽倾向于比宽沟槽更快地填充。这导致一旦所有沟槽都被填充，就会形成非平面表面。 本发明通过两步进行电沉积来解决这个问题。 在第一步骤期间使用的电镀槽在针对第二步骤期间使用的电镀槽进行优化以优化用于填充窄沟槽的情况下进行优化，以优化填充宽的沟槽。 最终的结果是具有平坦表面的最终层，其中所有的沟槽被正确填充。

公开(公告)号：US20050164495A1

公开(公告)日：2005-07-28

申请号：US10763306

申请日：2004-01-23

申请人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

发明人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Ming-Wei Lin

IPC分类号： C25D3/38 ,  C25D5/10 ,  C25D7/12 ,  H01L21/288 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H05K3/42

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/7684 ,  H01L21/76877 ,  H05K3/423

摘要： Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.

摘要翻译： 衬底中的窄沟槽倾向于比宽沟槽更快地填充。这导致一旦所有沟槽都被填充，就会产生非平面表面。 本发明通过两步进行电沉积来解决这个问题。 在第一步骤期间使用的电镀槽在针对第二步骤期间使用的电镀槽进行优化以优化用于填充窄沟槽的情况下进行优化，以优化填充宽的沟槽。 最终的结果是具有平坦表面的最终层，其中所有的沟槽被正确填充。

公开(公告)号：US07544281B2

公开(公告)日：2009-06-09

申请号：US11119183

申请日：2005-04-28

申请人： Ming-Wei Lin ,  Ming-Hsing Tsai

发明人： Ming-Wei Lin ,  Ming-Hsing Tsai

IPC分类号： C25D5/02

CPC分类号： C25D17/06 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  H01L21/2885

摘要： An electrochemical plating apparatus and method for facilitating uniform current distribution across a wafer during loading into an ECP (electrochemical plating) apparatus is disclosed. The apparatus includes a bath container for containing a bath solution, an anode provided in the bath container, a cathode ring for supporting a wafer in the bath container and a current source electrically connected to the anode and the cathode ring. According to the method, a voltage potential is applied to the cathode ring as it is immersed into the solution and prior to immersion of the wafer in the solution, thereby facilitating a substantially uniform plating current across the wafer upon immersion of the wafer.

摘要翻译： 公开了一种用于在装载到ECP（电化学电镀）装置中时促进在晶片上均匀分布电流的电化学电镀装置和方法。 该装置包括用于容纳浴溶液的浴容器，设置在浴容器中的阳极，用于在浴容器中支撑晶片的阴极环和与阳极和阴极环电连接的电流源。 根据该方法，当阴极环浸入溶液中并且在将晶片浸入溶液之前，电压电势被施加到阴极环上，从而有助于在晶片浸入时跨晶片的基本均匀的电镀电流。

公开(公告)号：US20100230816A1

公开(公告)日：2010-09-16

申请号：US12787559

申请日：2010-05-26

申请人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

摘要翻译： 提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。 提供了一种半导体器件，包括衬底。 其中具有至少一个导电特征的电介质层覆盖在衬底上。 绝缘覆盖层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。

公开(公告)号：US07597787B2

公开(公告)日：2009-10-06

申请号：US11072137

申请日：2005-03-04

申请人： Hung-Wen Su ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Ming-Hsing Tsai

IPC分类号： C25D3/06

CPC分类号： C25D17/001 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/76841

摘要： Methods and apparatuses for electrochemically depositing a metal layer onto a substrate. An electrochemical deposition apparatus comprises a substrate holder assembly including a substrate chuck and a relatively soft cathode contact ring. The cathode contact ring comprises an inner portion and an outer portion, wherein the inner portion directly contacts the substrate. An anode is disposed in an electrolyte container. A power supply connects the substrate holder assembly and the anode.

摘要翻译： 将金属层电化学沉积到基底上的方法和装置。 一种电化学沉积设备包括一个衬底保持器组件，该衬底保持器组件包括衬底卡盘和相对软的阴极接触环 阴极接触环包括内部部分和外部部分，其中内部部分直接接触基板。 阳极设置在电解质容器中。 电源连接衬底保持器组件和阳极。

公开(公告)号：US07026244B2

公开(公告)日：2006-04-11

申请号：US10637105

申请日：2003-08-08

申请人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

发明人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC分类号： H01C23/48

CPC分类号： H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

摘要翻译： 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US06759750B2

公开(公告)日：2004-07-06

申请号：US10623910

申请日：2003-07-18

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai

IPC分类号： H01L2348

CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

摘要翻译： 一种用于在半导体制造中集成低K材料的方法。 该方法开始于提供其上具有介电层的半导体结构，其中介电层包含有机低K材料。 图案化电介质层以形成柱状开口。 在半导体结构上沉积柱层; 从而用柱层填充柱状开口。 柱层被平坦化以形成嵌入在所述介电层中的柱。 柱层包括具有良好的热稳定性，良好的结构强度和旋涂后端材料的良好的粘合性的材料，提高半导体制造中的有机，低K电介质的可制造性。 在一个实施例中，在形成双镶嵌层间接触之前形成柱。 在另一个实施方案中，柱与层间接触同时形成。