公开(公告)号：US20090104747A1

公开(公告)日：2009-04-23

申请号：US12046470

申请日：2008-03-12

申请人： Shian-Jyh Lin

发明人： Shian-Jyh Lin

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/0207

摘要： A method for fabricating deep trench DRAM array is disclosed. A substrate having thereon a memory array area is provided. An array of deep trench patterns is formed in the memory array area. The deep trench (DT) capacitor patterns include first dummy DT patterns in a first column, second dummy DT patterns in a first row and a plurality of effective DT capacitor patterns. Each of the first dummy DT patterns has an extended width (W) along a first direction, which is greater than or equal to a photomask's shift tolerance. Each of the second dummy DT patterns has an extended length (L) along a second direction, which is greater than or equal to the photomask's shift tolerance. The first direction is normal to the second direction.

摘要翻译： 公开了一种用于制造深沟槽DRAM阵列的方法。 提供其上具有存储器阵列区域的衬底。 在存储器阵列区域中形成深沟槽图形的阵列。 深沟槽（DT）电容器图案包括第一列中的第一虚拟DT图案，第一行中的第二虚设DT图案和多个有效DT电容器图案。 第一虚拟DT图案中的每个图案沿着第一方向具有大于或等于光掩模的偏移容限的扩展宽度（W）。 第二虚拟DT图案中的每一个沿着第二方向具有大于或等于光掩模的移动公差的延伸长度（L）。 第一个方向与第二个方向正交。

公开(公告)号：US20090068813A1

公开(公告)日：2009-03-12

申请号：US11964516

申请日：2007-12-26

申请人： Shian-Jyh Lin ,  Shun-Fu Chen ,  Tse-Chuan Kuo ,  An-Hsiung Liu

发明人： Shian-Jyh Lin ,  Shun-Fu Chen ,  Tse-Chuan Kuo ,  An-Hsiung Liu

IPC分类号： H01L21/02

CPC分类号： H01L29/945 ,  H01L23/544 ,  H01L27/1087 ,  H01L29/66181 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

摘要翻译： 一种制造半导体器件的方法包括提供具有器件区域和测试键区域的半导体衬底。 在器件区域中形成第一沟槽，并且在测试键区域中形成第二沟槽。 在第一和第二沟槽中形成具有第一蚀刻选择性的导电层。 在第一方向上执行第一注入工艺以在导电层中同时并分别在器件区域和测试键区中形成具有第一杂质和未掺杂区的第一掺杂区。 在第二沟槽中执行第二注入工艺以在导电层中形成具有第二杂质的第二掺杂区，其中第二沟槽中的导电层具有高于第一蚀刻选择性的第二蚀刻选择性。

公开(公告)号：US07446355B2

公开(公告)日：2008-11-04

申请号：US11556170

申请日：2006-11-03

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US20080012066A1

公开(公告)日：2008-01-17

申请号：US11536686

申请日：2006-09-29

申请人： Shian-Jyh Lin

发明人： Shian-Jyh Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823487 ,  H01L27/10876 ,  H01L29/66666

摘要： A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.

摘要翻译： 提供一种用于制造垂直沟道晶体管器件的方法。 在由衬垫氮化物层和衬垫氧化物层组成的电介质堆叠中形成开口。 进行多个外延硅生长和干蚀刻工艺以在开口中形成漏极，垂直沟道和源极。 随后，在垂直沟道上形成侧壁栅极电介质和侧壁栅电极。 本发明适用于特别适用于非常高密度的沟槽电容器DRAM器件的动态随机存取存储器（DRAM）器件。

公开(公告)号：US20070264772A1

公开(公告)日：2007-11-15

申请号：US11685756

申请日：2007-03-13

申请人： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

发明人： Yu-Pi Lee ,  Shian-Jyh Lin ,  Jar-Ming Ho

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L21/28061 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66545

摘要： A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US20050245040A1

公开(公告)日：2005-11-03

申请号：US11039843

申请日：2005-01-24

申请人： Sam Liao ,  Shian-Jyh Lin ,  Chia-Sheng Yu

发明人： Sam Liao ,  Shian-Jyh Lin ,  Chia-Sheng Yu

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： A method for forming a deep trench capacitor mainly utilizes a liquid phase deposition (LPD) oxide to form a collar oxide layer in the trench, followed by forming a conductive layer serving as an upper electrode of the deep trench capacitor, thereby avoiding collar oxide residue in the conductive layer and thus forming good electrical connection. And, the method of the present invention does not need a dry etch to remove the unnecessary collar oxide layer such that the process can be simplified.

摘要翻译： 形成深沟槽电容器的方法主要利用液相沉积（LPD）氧化物在沟槽中形成环状氧化物层，随后形成用作深沟槽电容器的上电极的导电层，从而避免环氧化物残留物 在导电层中，从而形成良好的电连接。 而且，本发明的方法不需要干蚀刻来去除不需要的环形氧化物层，从而可以简化该方法。

公开(公告)号：US20050239282A1

公开(公告)日：2005-10-27

申请号：US10940772

申请日：2004-09-15

申请人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Chia-Sheng Yu

发明人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Chia-Sheng Yu

IPC分类号： H01L21/4763 ,  H01L21/60

CPC分类号： H01L21/76897

摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of forming a first insulating layer comprising a nitride along a profile of a gate structure and a junction region, forming a temporary layer comprising a doped oxide on the first insulating layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulating layer comprising an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact in the contact hole.

摘要翻译： 一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。 该方法包括以下步骤：沿着栅极结构和结区的轮廓形成包括氮化物的第一绝缘层，在第一绝缘层上形成包括掺杂氧化物的临时层，通过执行临时层去除一部分临时层 用掩模选择性地蚀刻氧化物，同时将临时层的插塞部分留在接合区域上，形成第二绝缘层，该第二绝缘层包括去除部分临时层的区域中的未掺杂的氧化物，通过执行 对未掺杂的氧化物进行选择性蚀刻以形成接触孔，在接触孔的底部除去第一绝缘层的一部分，以及在接触孔中形成导电接触。

公开(公告)号：US20050221616A1

公开(公告)日：2005-10-06

申请号：US10816820

申请日：2004-04-05

申请人： Meng-Hung Chen ,  Shian-Jyh Lin

发明人： Meng-Hung Chen ,  Shian-Jyh Lin

IPC分类号： B44C1/22 ,  H01L21/308 ,  H01L21/311 ,  H01L21/334 ,  H01L21/8242

CPC分类号： H01L29/66181 ,  H01L21/3081 ,  H01L27/1087

摘要： A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of the silicon substrate, the first trench having a first depth; forming a nitride layer on the surfaces of the whole structure; forming a second trench in the first trench downward, the second trench having a second depth greater than the first depth; forming another nitride layer on the surfaces of the whole structure; and forming a third trench in the second trench downward, the third trench having a third depth greater than the second depth. The method of the present invention can make the whole trench have better etch uniformity, thereby obtaining good electrical performance.

摘要翻译： 形成深沟槽结构的方法包括以下步骤：提供硅衬底; 在所述硅衬底上形成预定图案的掩模层以暴露所述硅衬底的一部分; 在所述硅衬底的暴露部分中形成第一沟槽，所述第一沟槽具有第一深度; 在整个结构的表面上形成氮化物层; 在所述第一沟槽中形成第二沟槽，所述第二沟槽具有大于所述第一深度的第二深度; 在整个结构的表面上形成另一个氮化物层; 以及在所述第二沟槽中向下形成第三沟槽，所述第三沟槽的第三深度大于所述第二深度。 本发明的方法可以使整个沟槽具有更好的蚀刻均匀性，从而获得良好的电性能。

公开(公告)号：US20050221560A1

公开(公告)日：2005-10-06

申请号：US11139450

申请日：2005-05-27

申请人： Yu-Sheng Shu ,  Yuan-Hsun Wu ,  Chung-Yuan Lee ,  Shian-Jyh Lin

发明人： Yu-Sheng Shu ,  Yuan-Hsun Wu ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F9/00 ,  H01L21/027 ,  H01L21/308 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/02

CPC分类号： H01L27/1087 ,  H01L21/3083 ,  H01L27/0207 ,  H01L27/10864

摘要： A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.

摘要翻译： 一种形成具有矩形沟槽的垂直存储器件的方法。 首先，提供由光致抗蚀剂层覆盖的基板。 接下来，通过掩模限定光致抗蚀剂层以形成矩形开口，其中掩模具有以预定间隔布置的两个矩形透明图案。 接下来，使用限定的光致抗蚀剂层作为掩模来蚀刻基板以形成单个矩形沟槽，然后除去光致抗蚀剂层。 最后，在矩形沟槽中依次形成沟槽电容器和垂直晶体管，以完成垂直存储器件。

公开(公告)号：US20050167721A1

公开(公告)日：2005-08-04

申请号：US10845909

申请日：2004-05-14

申请人： Shian-Jyh Lin ,  Yu-Sheng Hsu

发明人： Shian-Jyh Lin ,  Yu-Sheng Hsu

IPC分类号： H01L21/334 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/732

CPC分类号： H01L29/66181 ,  H01L27/10841 ,  H01L27/10867

摘要： A memory cell with a vertical transistor has a semiconductor silicon substrate with a deep trench, in which the deep trench has a first sidewall region and a second sidewall region. A first insulating layer is formed overlying the first sidewall region. A second insulating layer is formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer. A gate electrode layer is sandwiched between the first insulating layer and the second insulating layer. A buried strap out-diffusion region is formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.

摘要翻译： 具有垂直晶体管的存储单元具有深沟槽的半导体硅衬底，其中深沟槽具有第一侧壁区域和第二侧壁区域。 第一绝缘层形成在第一侧壁区域的上方。 第二绝缘层形成为覆盖第二侧壁区域，其中第一绝缘层的厚度大于第二绝缘层的厚度。 栅电极层夹在第一绝缘层和第二绝缘层之间。 掩埋带外扩散区域形成在邻近第二侧壁区域的衬底中，其中掩埋带外延扩散区域位于第二绝缘层的下部附近。